PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 22

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

X
X
X
X
X
X
7
1
0
2 0 Configuration Registers
Note When FER4
2 5 2 Function Address Register (FAR Index
This register selects the ISA I O address range to which
each peripheral function responds
Bits 0 1 These bits select the parallel port address as
Note The interrupt assigned to this address can be changed to IRQ7 by
Bits 2–5 These bits determine which ISA I O address range
Bit
Bit 5
1
0
0
1
1
0
1
X
X
or 372h takes place This pulse is delayed by 25 ns–80 ns after the leading edge of IOW and its leading edge can be used to clock data into an external latch
(e g 74LS175) Address 3F2h is used if the FDC is located at the primary address (FER5
secondary address (FER5
setting Bit 3 of the Power and Test Register (PTR)
X
X
6
X
1
X
X
0
X
shown in Table 2-5
is associated with each UART (see Table 2-6 and
Table 2-7)
Digital Output Register
TABLE 2-4 Primary and Secondary
TABLE 2-5 Parallel Port Addresses
5
X
1
X
X
X
0
X
X
Bit
0
0
1
0
1
Bit 7
e
X
X
0
1
Drive Address Selection
1 MTR1 presents a pulse that is the inverted image of the IOW strobe This inverted pulse is active whenever an I O write to address 3F2h
4
1
X
X
X
0
X
X
X
LPTB (378–37F)
LPTA (3BC–3BE)
LPTC (278–27F)
Reserved
X
X
X
X
X
X
X
X
3
Address
Parallel
e
Drive
FDC
FDC
Port
IDE
IDE
TABLE 2-3 Encoded Drive and Motor Pin Information (FER 4
1)
X
X
X
X
X
X
X
X
2
1
0
0
1
1
0
0
1
1
1F0–7h 3F6–7h
170–7h 376–7h
PC-AT Mode
0
0
1
0
1
0
1
0
1
Secondary
Secondary
Primary
Primary
3F0– 7h
3F0– 7h
IRQ5 (Note)
(CTR4
TRI-STATE
Interrupt
(Continued)
PC-AT
e
MTR1
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
IRQ7
IRQ5
01h)
e
0)
Drive Control Pins
MTR0
0
0
0
0
1
1
1
1
22
Bits 6 7 These bits select the addresses that are used for
Note COM3 and COM4 addresses are determined by Bits 6 and 7
DR1
TABLE 2-8 Address Selection for COM3 and COM4
Bit 7
0
0
1
1
0
0
1
1
0
0
1
1
Bit 3
Bit 5
TABLE 2-6 COM Port Selection for UART1
TABLE 2-7 COM Port Selection for UART2
0
0
1
1
0
0
1
1
COM3 and COM4 (see Table 2-8)
e
DR0
0
1
0
1
0
1
0
1
0) and address 372h is used if the FDC is located at the
Bit 6
FAR
FAR
0
1
0
1
Activate Drive 0 and Motor 0
Activate Drive 1 and Motor 1
Activate Drive 2 and Motor 2
Activate Drive 3 and Motor 3
Activate Drive 0 and Deactivate Motor 0
Activate Drive 1 and Deactivate Motor 1
Activate Drive 2 and Deactivate Motor 2
Activate Drive 3 and Deactivate Motor 3
Bit 2
Bit 4
0
1
0
1
0
1
0
1
COM3 IRQ4
e
3E8 –Fh
2E8 –Fh
338–Fh
220–7h
1)
Decoded Functions
1 (3F8-F)
2 (2F8-F)
3 (Table 2-8)
4 (Table 2-8)
1 (3F8-F)
2 (2F8-F)
3 (Table 2-8)
4 (Table 2-8)
UART1
UART2
COM
COM
COM4 IRQ3
2E8–Fh
2E0–7h
238–Fh
228 –Fh