PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 64

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

5 0 FDC Functional Description
Specify command values will be don’t cares so they must
be reinitialized The major default conditions are FIFO dis-
abled FIFO threshold
Drive Polling enabled
A software reset can be performed through the Digital Out-
put Register or Data Rate Select Register The DSR reset
bit is self-clearing while the DOR reset bit is not self-clear-
ing If the LOCK bit in the Lock command was set to a 1
previous to the software reset the FIFO THRESH and
PRETRK parameters in the Configure command will be re-
tained In addition the FWR FRD and BST parameters in
the Mode command will be retained if LOCK is set to 1 This
function eliminates the need for total reinitialization of the
controller after a software reset
After a hardware (assuming the FDC is enabled in the FER)
or software reset the Main Status Register is immediately
available for read access by the P It will return a 00h value
until all the internal registers have been updated and the
data separator is stabilized When the controller is ready to
receive a command byte the MSR will return a value of 80h
(Request for Master bit is set) The MSR is guaranteed to
return the 80h value within 2 5 s after a hardware or soft-
ware reset All other user addressable registers other than
the Main Status Register and Data Register (FIFO) can be
accessed at any time even while the part is in reset
6 0 Serial Ports
Each of these serial ports functions as a serial data input
output interface in a microcomputer system The system
software determines the functional configuration of the
UARTs via an 8-bit bidirectional data bus
The UARTs are completely independent They perform
serial-to-parallel conversion on data characters received
from a peripheral device or a MODEM and parallel-to-serial
conversion on data characters received from the CPU The
CPU can read the complete status of either UART at any
time during the functional operation Status information re-
ported includes the type and condition of the transfer opera-
tions being performed by the UART as well as any error
conditions (parity overrun framing or break interrupt)
The UARTs have programmable baud rate generators that
are capable of dividing the internal reference clock by divi-
sors of 1 to (2
the transmitter logic Provisions are also included to use this
16x clock to drive the receiver logic The UARTs have com-
plete MODEM-control capability and a prioritized interrupt
system Interrupts can be programmed to the user’s require-
ments minimizing the computing required to handle the
communications link
6 1 SERIAL PORT REGISTERS
Two identical register sets one for each channel are in the
PC87332 All register descriptions in this section apply to
the register sets in both channels See Table 6-1
6 2 LINE CONTROL REGISTER (LCR)
The system programmer uses the Line Control Register
(LCR) to specify the format of the asynchronous data com-
munications exchange and set the Divisor Latch Access bit
This is a read and write register Table 6-2 shows the con-
tents of the LCR Details on each bit follow
FIGURE 6-1 PC87332 Composite Serial Data
16
–1) and producing a 16x clock for driving
e
0 Implied Seeks disabled and
Read Write
TL C 11930– 11
(Continued)
64
Bits 0 1 These two bits specify the number of data bits in
Bit 2
Bit 3
Bit 4
Bit 5
DLAB
0
0
0
X
X
X
X
X
1
1
each transmitted or received serial character The
encoding of bits 0 and 1 is as follows
This bit specifies the number of Stop bits transmit-
ted with each serial character If it is 0 one Stop
bit is generated in the transmitted data If it is 1
when a 5-bit data length is selected one and a
half Stop bits are generated If it is 1 when either a
6- 7- or 8-bit word length is selected two Stop
bits are generated The receiver checks the first
Stop bit only regardless of the number of Stop
bits selected
This bit is the Parity Enable bit When it is 1 a
Parity bit is generated (transmit data) or checked
(receive data) between the last data bit and the
following Stop bit of the serial data (The Parity bit
is used to produce an even or odd number of 1s
when the data bits and the Parity bit are summed )
This bit is the Even Parity Select bit When parity is
enabled and bit 4 is 0 an odd number of logic 1s
is transmitted or checked in the data word bits and
Parity bit When parity is enabled and bit 4 is a 1
an even number of logic 1s is transmitted or
checked
This bit is the Stick Parity bit When parity is en-
abled it is used in conjunction with bit 4 to select
Mark or Space Parity When LCR bits 3 4 and 5
are 1 the Parity bit is transmitted and checked as a
0 (Space Parity) If bits 3 and 5 are 1 and bit 4 is a
0 then the Parity bit is transmitted and checked as
1 (Mark Parity) If bit 5 is 0 Stick Parity is disabled
A2
0
0
0
0
1
1
1
1
0
0
Bit 1
Register Addresses (AEN
0
0
1
1
TABLE 6-1 PC87332 UART
A1
0
0
1
1
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
Bit 0
0
1
0
1
Receiver Buffer (Read)
Transmitter Holding (Write)
Interrupt Enable
Interrupt Identification (Read)
FIFO Control (Write)
Line Control
MODEM Control
Line Status
MODEM Status
Scratch
Divisor Latch
(Least Significant Byte)
Divisor Latch
(Most Significant Byte)
Selected Register
Data Length
5 Bits
6 Bits
7 Bits
8 Bits
e
0)