PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 31

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

3 0 FDC Register Description
D4–2
D1 –0
Bits 4 3 2
Data Rate
TABLE 3-6 Default Precompensation Delays
500 kbps
300 kbps
250 kbps
TABLE 3-5 Write Precompensation Delays
111
001
010
011
100
101
110
000
Precompensation Select These three bits select
the amount of write precompensation the floppy
controller uses on the WDATA disk interface output
Table 3-5 shows the amount of precompensation
used for each bit pattern In most cases the default
values (Table 3-6) can be used however alternate
values can be chosen for specific types of drives
and media Track 0 is the default starting track num-
ber for precompensation The starting track number
can be changed in the Configure command
Data Rate Select 1 0 These bits determine the
data rate for the floppy controller See Table 3-7 for
the corresponding data rate for each D1 0 value
pair The data rate select bits are unaffected by a
software reset and are set to 250 kbps after a hard-
ware reset
2 Mbps
1 Mbps
TUP Bit 0
DEFAULT
24 MHz
125 0 ns
166 7 ns
208 3 ns
250 0 ns
Precompensation Delay
41 7 ns
83 3 ns
0 0 ns
Precompensation Delay
(24 MHz and 48 MHz)
e
1
125 0 ns
125 0 ns
125 0 ns
20 8 ns
41 7 ns
TUP Bit 1
DEFAULT
48 MHz
104 2 ns
125 0 ns
20 8 ns
41 7 ns
62 5 ns
83 3 ns
0 0 ns
(Continued)
e
1
31
3 1 7 Data Register (FIFO)
The FIFO (read write) is used to transfer all commands
data and status between the
Command Phase the P writes the command bytes into the
FIFO after polling the RQM and DIO bits in the MSR During
the Result Phase the
FIFO after polling the RQM and DIO bits in the MSR
Enabling the FIFO and setting the FIFO threshold is done
via the Configure command If the FIFO is enabled only the
Execution Phase byte transfers use the 16-byte FIFO The
FIFO is always disabled during the Command and Result
Phases of a controller operation A software reset will not
disable enabled FIFO if the Lock bit is set in the Lock Com-
mand After a hardware reset the FIFO is disabled to main-
tain compatibility with PC-AT systems
The 16-byte FIFO can be used for DMA Interrupt or soft-
ware polling type transfers during the execution of a read
write format or scan command In addition the FIFO can
be put into a Burst or Non-Burst mode with the Mode com-
mand In the Burst mode DRQ or IRQ6 remains active until
all of the bytes have been transferred to or from the FIFO In
the Non-Burst mode DRQ or IRQ6 is deasserted for 350 ns
to allow higher priority transfer requests to be serviced
This feature is not tested
Bit 1
TUP
0
0
0
0
1
1
1
1
TABLE 3-7 Data Rate Select Encoding
Data Rate Select
1
1
0
0
1
1
0
0
1
P reads the result bytes from the
P and the FDC During the
0
1
0
1
0
1
0
1
0
500 kbps
300 kbps
250 kbps
Read Write
2 Mbps
1 Mbps
Illegal
Illegal
Illegal
MFM