AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 28

• Manufacturer Part Number: AM49BDS640AHD8I
• Description: Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
• Manufacturer: SPANSION [SPANSION]

COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations.
p a g e 3 6
sequences. Writing incorrect address and data values
or writing them in the improper sequence may place the
device in an unknown state. The system must write the
reset command to return the device to reading array
data. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read data
from any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data from any non-erase-suspended sector
within the same bank. See the
Resume Commands” section on page 32
information.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the
Command” section on page 29
See also
ation (Non-Burst)” section on page 12
ments for Synchronous (Burst) Read Operation”
section on page 12
chronous Read and Synchronous/Burst Read tables
provide the read parameters, and
chronous Burst Mode Read (rising active CLK),” on
page
on page
with Latched Addresses,” on page 58
Set Configuration Register Command Se-
quence
The device uses a configuration register to set the
various burst parameters: number of wait states, burst
read mode, active clock edge, RDY configuration, and
synchronous mode active. The configuration register
must be set before the device will enter burst mode.
The configuration register is loaded with a three-cycle
command sequence. The first two cycles are standard
unlock sequences. On the third cycle, the data should
be C0h, address bits A11–A0 should be 555h, and
26
49,
50, and
“Requirements for Asynchronous Read Oper-
Figure 15, “Synchronous Burst Mode Read,”
d e f i n e s t h e va li d r e g i s t e r co m m a n d
Table 15, “Command Definitions,” on
Figure 28, “Asynchronous Mode Read
for more information. The Asyn-
“Erase Suspend/Erase
for more information.
A D V A N C E
Figure 13, “CLK Syn-
show the timings.
and
“Require-
for more
“Reset
Am49BDS640AH
I N F O R M A T I O N
address bits A19–A12 set the code to be latched. The
device will power up or after a hardware reset with the
default setting, which is in asynchronous mode. The
register must be set before the device can enter syn-
chronous mode. The configuration register can not be
changed during device operations (program, erase, or
sector lock).
Read Mode Setting
On power-up or hardware reset, the device is set to be
in asynchronous read mode. This setting allows the
system to enable or disable burst mode during system
operations. Address A19 determines this setting: “1” for
asynchronous mode, “0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the
device of the number of clock cycles that must elapse
after AVD# is driven active before data will be available.
This value is determined by the input frequency of the
device. Address bits A14–A12 determine the setting
(see
page
The wait state command sequence instructs the device
to set a particular number of clock cycles for the initial
access in burst mode. The number of wait states that
should be programmed into the device is directly
related to the clock frequency.
Figure 3. Synchronous/Asynchronous State
Configuration Register
Table 10, “Programmable Wait State Settings,” on
27).
Synchronous Mode
Set Burst Mode
Command for
(D15 = 0)
Asynchronous Read
Synchronous Read
Hardware Reset
Diagram
Mode Only
Mode Only
Power-up/
Configuration Register
Asynchronous Mode
Set Burst Mode
Command for
December 5, 2003
(D15 = 1)