AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 50
AM49BDS640AHD8I
Manufacturer Part Number
AM49BDS640AHD8I
Description
Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49BDS640AHD8I.pdf
(84 pages)
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AC CHARACTERISTICS
Synchronous/Burst Read
Note:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
48
JEDEC
Parameter
Standard
t
t
t
t
t
t
BACC
t
t
t
t
t
t
RDYS
RACC
t
t
t
t
t
t
t
t
t
IACC
IACC
t
t
RCC
ACS
ACH
BDH
CEZ
OEZ
CES
AAS
AAH
CAS
AVC
AVD
ACC
CKA
CKZ
OES
CR
OE
Description
Latency (Even address in Reduced wait-state
Handshake mode)
Latency (Standard Handshake or Odd
address in Reduced wait-state Handshake
mode
Burst Access Time Valid Clock to Output
Delay
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Output Enable to Output Valid
Chip Enable to High Z
Output Enable to High Z
CE# Setup Time to CLK
RDY Setup Time to CLK
Ready Access Time from CLK
Address Setup Time to AVD# (Note 1)
Address Hold Time to AVD# (Note 1)
CE# Setup Time to AVD#
AVD# Low to CLK
AVD# Pulse
Access Time
CLK to access resume
CLK to High Z
Output Enable Setup Time
Read cycle for continuous suspend
A D V A N C E
Am49BDS640AH
I N F O R M A T I O N
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
66 MHz
56
71
11
11
11
11
10
50
11
4
6
3
8
8
4
4
4
6
4
8
4
0
1
54 MHz
87.5
13.5
13.5
13.5
13.5
13.5
December 5, 2003
69
10
10
12
55
10
5
5
5
7
4
5
5
7
5
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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