AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 70

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AM49BDS640AHD8I

Manufacturer Part Number
AM49BDS640AHD8I
Description
Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
Manufacturer
SPANSION [SPANSION]
Datasheet
AC CHARACTERISTICS
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one
68
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
CE#
CLK
AVD#
Addresses
OE#
Data
RDY
WE#
DQ6
DQ2
toggle bits will stop toggling.
clock cycle before data.
Embedded
Erasing
Enter
V A
Figure 39. Synchronous Data Polling Timings/Toggle Bit Timings
Erase
Suspend
Erase
A D V A N C E
Erase Suspend
t
IACC
Read
Figure 40. DQ2 vs. DQ6
Suspend Program
Status Data
Enter Erase
Am49BDS640AH
I N F O R M A T I O N
Suspend
Program
Erase
V A
Erase Suspend
Read
Resume
Erase
t
IACC
Erase
December 5, 2003
Status Data
Complete
Erase

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