AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 5

• Manufacturer Part Number: AM49BDS640AHD8I
• Description: Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
• Manufacturer: SPANSION [SPANSION]

GENERAL DESCRIPTION
The Am49BDS640AH is a 64 Mbit, 1.8 Volt-only, simulta-
neous Read/Write, Burst Mode Flash memory device, orga-
nized as 4,194,304 words of 16 bits each. This device uses a
single V
memory array. A 12.0-volt V
faster program performance if desired. The device can also
be programmed in standard EPROM programmers.
At 66 MHz, the device provides a burst access of 11 ns at 30
pF with a latency of 56 ns at 30 pF. At 54 MHz, the device
provides a burst access of 13.5 ns at 30 pF with a latency of
69ns at 30 pF. The device operates within the industrial tem-
perature range of -40°C to +85°C.
The Simultaneous Read/Write architecture provides simul-
taneous operation by dividing the memory space into four
banks. The device can improve overall system performance
by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank, with zero latency. This releases the system from wait-
ing for the completion of program or erase operations.
The device is divided as shown in the following table:
The VersatileIO™ (V
the voltage levels that the device generates at its data out-
puts and the voltages tolerated at its data inputs to the same
voltage level that is asserted on the V
The device uses Chip Enable (CE#), Write Enable (WE#),
Address Valid (AVD#) and Output Enable (OE#) to control
asynchronous read and write operations. For burst opera-
tions, the device additionally requires Ready (RDY), and
Clock (CLK). This implementation allows easy interface with
minimal glue logic to a wide range of microprocessors/micro-
controllers for high performance read operations.
The burst read mode feature gives system designers flexibil-
ity in the interface to the device. The user can preset the
burst length and wrap through the same memory space, or
read the flash array in continuous mode.
The clock polarity feature provides system designers a
choice of active clock edges, either rising or falling. The ac-
tive clock edge initiates burst accesses and determines
when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard. Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
December 5, 2003
Bank
CC
C
D
A
B
of 1.65 to 1.95 V to read, program, and erase the
IO
) control allows the host system to set
Quantity
15
48
48
15
HH
8
8
on ACC may be used for
A D V A N C E
IO
pin.
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
4 Kwords
Size
Am49BDS640AH
I N F O R M A T I O N
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The hardware RESET# pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read boot-up firm-
ware from the Flash memory device.
The host system can detect whether a program or erase op-
eration is complete by using the device status bit DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program
or erase cycle has been completed, the device automatically
returns to reading array data.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low V
tector that automatically inhibits write operations during
power transitions. The device also offers two types of data
protection at the sector level. When at V
four highest and four lowest boot sectors.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both modes.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunnelling. The data is programmed using
hot electron injection.
IL
, WP# locks the
CC
de-
3