AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet - Page 56

• Manufacturer Part Number: AM49BDS640AHD8I
• Description: Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
• Manufacturer: SPANSION [SPANSION]

AC CHARACTERISTICS
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) RDY goes low during the two-cycle latency during a boundary crossing.
2) RDY stays high when a burst sequence crosses no boundaries.
Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) Burst suspend during the initial synchronous access
2) Burst suspend after one clock cycle following the initial synchronous access
54
Addresses
Addresses
Data(2)
Data(1)
RDY(2)
RDY(1)
OE#(1)
Data(1)
RDY(1)
OE#(2)
RDY(2)
Data(2)
AVD#
OE#
CLK
AVD#
CLK
A(n)
Figure 23. Standard Handshake Burst Suspend at or after Inital Access
A(n)
1
Figure 22. Standard Handshake Burst Suspend prior to Inital Access
1
2
2
t
ACC
t
3
ACC
A D V A N C E
3
4
4
t
OES
5
t
5
OES
Am49BDS640AH
Suspend
t
t
6
RACC
RACC
I N F O R M A T I O N
6
t
CKA
7
t
RACC
D(n)
D(n)
Suspend
7
t
OES
x
t
RACC
t
CKZ
D(n+1)
8
t
Resume
x+1
OES
t
CKA
D(n)
D(n)
t
RACC
9
t
RACC
x+2
D(n+1)
D(n+1)
x+3
D(n+2)
D(n+2)
x+4
x
D(n+3)
t
RACC
t
RACC
3F
x+5
Resume
x+1
t
OES
D(n+4)
t
December 5, 2003
CKA
3F
D(n+1)
D(n)
x+6
x+2
D(n+5)
D(3F)
D(n+1)
D(n+2)
x+7
x+3
D(n+6)
D(40)
x+8