OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 118

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OR3T125-5BA352

Manufacturer Part Number
OR3T125-5BA352
Description
3C and 3T Field-Programmable Gate Arrays
Manufacturer
AGERE [Agere Systems]
Datasheet
ORCA Series 3C and 3T FPGAs
Timing Characteristics
118
MPI_RW (RD/WR)
MPI_RW (RD/WR)
MPI_STRB (TS)
MPI_STRB (TS)
MPI_ACK (TA)
MPI_ACK (TA)
MPI_BI (BI)
MPI_BI (BI)
URDWRN
CS0, CS1
URDWRN
CS0, CS1
MPI_CLK
MPI_CLK
UA[3:0]
UA[3:0]
D[7:0]
A[4:0]
D[7:0]
A[4:0]
(continued)
Figure 70. MPI PowerPC Internal Write Timing
Figure 69. MPI PowerPC Internal Read Timing
URDWR_DEL
UA_DEL
UA_DEL
CS_SET
RW_SET
A_SET
CS_SET
RW_SET
A_SET
WD_SET
URDWR_DEL
UEND_SET
RDA_DEL
TA_DEL
TA_DEL
BI_DEL
BI_DEL
RW_HLD
RDS_HLD
RDS_SET
WD_HLD
RW_HLD
A_HLD
CS_HLD
CS_HLD
A_HLD
TA_DELZ
TA_DEL
BI_DEL
TA_DEL
BI_DEL
TA_DELZ
BI_DELZ
BI_DELZ
Lucent Technologies Inc.
RDA_HLD
Data Sheet
June 1999
5-5832(F).c
5-5840(F).e

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