OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 85

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
FPGA States of Operation
Prior to becoming operational, the FPGA goes through
a sequence of states, including initialization, configura-
tion, and start-up. Figure 49 outlines these three FPGA
states.
Lucent Technologies Inc.
YES
Figure 49. FPGA States of Operation
– CONFIGURATION DATA FRAME
– M[3:0] MODE IS SELECTED
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
– CLEAR CONFIGURATION
– INIT LOW, HDC HIGH, LDC LOW
WRITTEN
NO
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
MEMORY
– POWER-ON TIME DELAY
ERROR
BIT
CONFIGURATION
INITIALIZATION
START-UP
OPERATION
POWERUP
RESET,
PRGM
INIT,
LOW
OR
NO
YES
RESET
PRGM
PRGM
LOW
LOW
OR
5-4529(F)
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When V
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR3Cxx, 2.2 V to 2.7 V for the
OR3Txxx), the I/Os are configured based on the con-
figuration mode, as determined by the mode select
inputs M[2:0]. A time-out delay is initiated when V
reaches between 3.0 V and 4.0 V (OR3Cxx) or 2.7 V to
3.0 V (OR3Txxx) to allow the power supply voltage to
stabilize. The
erup, if V
25 ms, the user should delay configuration by inputting
a low into
than the recommended minimum operating voltage
(4.75 V for OR3Cxx commercial devices and 3.0 V for
OR3Txxx devices).
At the end of initialization, the default configuration
option is that the configuration RAM is written to a low
state. This prevents shorts prior to configuration. As a
configuration option, after the first configuration (i.e., at
reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first. The
active-low, open-drain initialization signal
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more
should be wire-ANDed. If
more FPGAs or an external device, the FPGA remains
in the initialization state.
the FPGAs are not yet initialized. After
for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.
The high during configuration (HDC), low during config-
uration (
the FPGA’s initialization and configuration states. HDC,
LDC
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
, and DONE can be used to provide control of
LDC
DD
INIT
does not rise from 2.0 V to V
), and DONE signals are active outputs in
,
INIT
ORCA Series 3C and 3T FPGAs
PRGM
and DONE outputs are low. At pow-
, or
INIT
RESET
INIT
can be used to signal that
is held low by one or
until V
DD
DD
INIT
DD
reaches the
INIT
is greater
in less than
goes high
is
INIT
DD
pins
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