OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 94

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes
Asynchronous Peripheral Mode
Figure 56 shows the connections needed for the asyn-
chronous peripheral mode. In this mode, the FPGA
system interface is similar to that of a microprocessor-
peripheral interface. The microprocessor generates the
control signals to write an 8-bit byte into the FPGA. The
FPGA control inputs include active-low
high CS1 chip selects and
selects can be cycled or maintained at a static level
during the configuration cycle. Each byte of data is writ-
ten into the FPGA’s D[7:0] input pins. D[7:0] of the
FPGA can be connected to D[7:0] of the microproces-
sor only if a standard prom file format is used. If a .bit or
.rbt file is used from ORCA Foundry, then the user must
mirror the bytes in the .bit or .rbt file OR leave the .bit or
.rbt file unchanged and connect D[7:0] of the FPGA to
D[0:7] of the microprocessor.
The FPGA provides an RDY/
cate that another byte can be loaded. A low on RDY/
BUSY
isters are not ready to receive data, and this pin must
be monitored to go high before another byte of data
can be written. The shortest time RDY/
occurs when a byte is loaded into the hold register and
the shift register is empty, in which case the byte is
immediately transferred to the shift register. The long-
est time for RDY/
byte is loaded into the holding register and the shift
register has just started shifting configuration data into
configuration RAM.
The RDY/
enabling the chip selects, setting
ing
enable for the D7 pin when
are not enabled to drive when
only act as input pins in asynchronous peripheral
mode. Optionally, the user can ignore the RDY/
status and simply wait until the maximum time it would
take for the RDY/
FPGA is ready for more data, before writing the next
data byte.
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94
RD
indicates that the double-buffered hold/shift reg-
low, where the
BUSY
status is also available on the D7 pin by
BUSY
BUSY
RD
to remain low occurs when a
line to go high, indicating the
input provides an output
WR
RD
BUSY
RD
and
is low. The D[6:0] pins
WR
is low and, therefore,
status output to indi-
RD
high, and apply-
inputs. The chip
BUSY
(continued)
CS0
and active-
is low
BUSY
Microprocessor Interface
The built-in MPI in Series 3 FPGAs is designed for use
in configuring the FPGA. Figure 57 and Figure 58 show
the glueless interface for FPGA configuration and read-
back from the PowerPC and i960 processors, respec-
tively. When enabled by the mode pins, the MPI
handles all configuration/readback control and hand-
shaking with the host processor. For single FPGA con-
figuration, the host sets the configuration control
register
reading that the
register, transfers data 8 bits at a time to the FPGA’s
D[7:0] input pins.
If configuring multiple FPGAs through daisy-chain
operation is desired, the MP_DAISY bit must be set in
the configuration control register of the MPI . Because
of the latency involved in a daisy-chain configuration,
the MP_HOLD_BUS bit may be set to zero rather than
one for daisy-chain operation. This allows the MPI to
acknowledge the data transfer before the configuration
information has been serialized and transferred on the
FPGA daisy-chain. The early acknowledgment frees
the host processor to perform other system tasks. Con-
figuring with the MP_HOLD_BUS bit at zero requires
that the host microprocessor poll the RDY/
the MPI status register and/or use the MPI interrupt
capability to confirm the readiness of the MPI for more
configuration data.
Figure 56. Asynchronous Peripheral Configuration
PROCESSOR
MICRO-
PRGM
DECODE LOGIC
CONTROLLER
bit to zero then back to a one and, after
ADDRESS
INIT
BUS
8
V
signal is high in the MPI status
DD
CS0
CS1
RD
WR
M2
M1
M0
PRGM
D[7:0]
RDY/BUSY
INIT
DONE
Lucent Technologies Inc.
(MPI)
SERIES
ORCA
FPGA
DOUT
CCLK
Mode
HDC
LDC
Data Sheet
June 1999
BUSY
TO DAISY-
CHAINED
DEVICES
bit of