OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 61

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Special Function Blocks
ORCA Series TAP Controller (TAPC)
The ORCA Series TAP controller (TAPC) is a 1149.1/
D1 compatible test access port controller. The 16 JTAG
state assignments from the IEEE 1149.1/D1 specifica-
tion are used. The TAPC is controlled by TCK and
TMS. The TAPC states are used for loading the IR to
allow three basic functions in testing: providing test
stimuli (Update-DR), test execution (Run-Test/Idle),
and obtaining test responses (Capture-DR). The TAPC
allows the test host to shift in and out both instructions
and test data/results. The inputs and outputs of the
TAPC are provided in the table below. The outputs are
primarily the control signals to the instruction register
and the data register.
Table 15. TAP Controller Input/Outputs
Lucent Technologies Inc.
Capture-DR
Update-DR
Capture-IR
Update-IR
TRESET
Shift-DR
Symbol
Shift-IR
Enable
Select
PRGM
TMS
PUR
TCK
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
Test Mode Select
Test Clock
Powerup Reset
BSCAN Reset
Test Logic Reset
Select IR (High); Select-DR (Low)
Test Data Out Enable
Capture/Parallel Load-DR
Capture/Parallel Load-IR
Shift Data Register
Shift Instruction Register
Update/Parallel Load-DR
Update/Parallel Load-IR
Function
(continued)
The TAPC generates control signals that allow capture,
shift, and update operations on the instruction and data
registers. In the capture operation, data is loaded into
the register. In the shift operation, the captured data is
shifted out while new data is shifted in. In the update
operation, either the instruction register is loaded for
instruction decode, or the boundary-scan register is
updated for control of outputs.
The test host generates a test by providing input into
the ORCA Series TMS input synchronous with TCK.
This sequences the TAPC through states in order to
perform the desired function on the instruction register
or a data register. Figure 39 provides a diagram of the
state transitions for the TAPC. The next state is deter-
mined by the TMS input value.
Figure 39. TAP Controller State Transition Diagram
1
0
TEST-LOGIC-
RUN-TEST/
RESET
IDLE
0
ORCA Series 3C and 3T FPGAs
1
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
1
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
SELECT-
0
0
1
0
1
1
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
1
PAUSE-IR
SELECT-
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
0
0
1
0
1
1
0
5-5370(F)
1
1
0
0
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