OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 16

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
Half-Logic Mode
Series 3 FPGAs are based upon a twin-quad architec-
ture in the PFUs. The byte-wide nature (eight LUTs,
eight latches/FFs) may just as easily be viewed as two
nibbles (two sets of four LUTs, four latches/FFs). The
two nibbles of the PFU are organized so that any nib-
ble-wide feature (excluding some softwired LUT topolo-
gies) can be swapped with any other nibble-wide
feature in another PFU. This provides for very flexible
use of logic and for extremely flexible routing. The half-
logic mode of the PFU takes advantage of the twin-
quad architecture and allows half of a PFU, K
associated latches/FFs, to be used in logic mode while
the other half of the PFU, K
FFs, is used in ripple mode. In half-logic mode, the
ninth FF may be used as a general-purpose FF or as a
register in the ripple mode carry chain.
Ripple Mode
The PFU LUTs can be combined to do byte-wide ripple
functions with high-speed carry logic. Each LUT has a
dedicated carry-out net to route the carry to/from any
adjacent LUT. Using the internal carry circuits, fast
arithmetic, counter, and comparison functions can be
implemented in one PFU. Similarly, each PFU has
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT)
ports for fast-carry routing between adjacent PFUs.
The ripple mode is generally used in operations on two
data buses. A single PFU can support an 8-bit ripple
function. Data buses of 4 bits and less can use the
nibble-wide ripple chain that is available in half-logic
mode. This nibble-wide ripple chain is also useful for
longer ripple chains where the length modulo 8 is four
or less. For example, a 12-bit adder (12 modulo 8 = 4)
can be implemented in one PFU in ripple mode (8 bits)
and one PFU in half-logic mode (4 bits), freeing half of
a PFU for general logic mode functions.
Each LUT has two operands and a ripple (generally
carry) input, and provides a result and ripple (generally
carry) output. A single bit is rippled from the previous
LUT and is used as input into the current LUT. For LUT
K
The CIN/FCIN data can come from either the fast-carry
routing (FCIN) or the PFU input (CIN), or it can be tied
to logic 1 or logic 0.
In the following discussions, the notations LUT K
and F[7:0]/F[3:0] are used to denote the LUT that pro-
vides the carry-out and the data outputs for full PFU
ripple operation (K
operation (K
diagram in Figure 6 shows full PFU ripple operation,
16
16
0
, the ripple input is from the PFU CIN or FCIN port.
3
, F[3:0]), respectively. The ripple mode
7
, F[7:0]) and half-logic ripple
[3:0]
and associated latches/
(continued)
[7:4]
7
and
/K
3
with half-logic ripple connections shown as dashed
lines.
The result output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
two operands are input into K
LUT. The result bits, one per LUT, are F[7:0]/F[3:0] (see
Figure 6). The ripple output from LUT K
routed on dedicated carry circuitry into any of four adja-
cent PLCs, and it can be placed on the PFU COUT/
FCOUT outputs. This allows the PLCs to be cascaded
in the ripple mode so that nibble-wide ripple functions
can be expanded easily to any length.
Result outputs and the carry-out may optionally be reg-
istered within the PFU. The capability to register the
ripple results, including the carry output, provides for
improved counter performance and simplified pipelin-
ing in arithmetic functions.
CIN/FCIN
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
Figure 6. Ripple Mode
K
K
K
K
K
K
K
K
7
6
5
4
3
2
1
0
C
C
Z
Lucent Technologies Inc.
[1] and K
D Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Z
7
/K
[0] of each
Data Sheet
June 1999
3
can be
Q3
Q2
REGCOUT
FCOUT
COUT
F7
Q7
F6
Q6
F5
Q5
F4
Q4
F3
F2
F1
Q1
F0
Q0
5-5755(F)