OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 2

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Contents
ORCA Series 3C and 3T FPGAs
Features ......................................................................1
System-Level Features................................................6
Description...................................................................7
Architecture .................................................................9
Programmable Logic Cells ........................................11
Programmable Input/Output Cells .............................36
High-Level Routing Resources..................................47
Clock Distribution Network ........................................50
Special Function Blocks ............................................54
Microprocessor Interface (MPI) .................................64
Programmable Clock Manager (PCM) ......................72
2
FPGA Overview ........................................................7
PLC Logic ..................................................................7
PIC Logic ...................................................................8
System Features .......................................................8
Routing ......................................................................8
Configuration .............................................................8
ORCA Foundry Development System ......................9
Programmable Function Unit ..................................11
Look-Up Table Operating Modes ............................13
Supplemental Logic and Interconnect Cell (SLIC) ..21
PLC Latches/Flip-Flops ...........................................25
PLC Routing Resources ..........................................27
PLC Architectural Description .................................34
5 V Tolerant I/O .......................................................37
PCI Compliant I/O ...................................................37
Inputs ......................................................................38
Outputs ....................................................................41
PIC Routing Resources ...........................................44
PIC Architectural Description ..................................45
Interquad Routing ....................................................47
Programmable Corner Cell Routing ........................48
PIC Interquad (MID) Routing ...................................49
PFU Clock Sources .................................................50
Clock Distribution in the PLC Array .........................51
Clock Sources to the PLC Array .............................52
Clocks in the PICs ...................................................52
ExpressCLK Inputs .................................................53
Selecting Clock Input Pins ......................................53
Single Function Blocks ............................................54
Boundary Scan ........................................................57
PowerPC System ....................................................65
i960 System ............................................................66
MPI Interface to FPGA ............................................67
MPI Setup and Control ............................................68
PCM Registers ........................................................73
Delay-Locked Loop (DLL) Mode .............................75
Phase-Locked Loop (PLL) Mode ............................76
PCM/FPGA Internal Interface .................................79
PCM Operation .......................................................79
PCM Detailed Programming ...................................80
PCM Applications ....................................................83
Table of Contents
Page
Contents
FPGA States of Operation........................................ 85
Configuration Data Format ...................................... 89
FPGA Configuration Modes...................................... 92
Absolute Maximum Ratings.................................... 100
Electrical Characteristics ........................................ 101
Timing Characteristics ............................................ 103
Input/Output Buffer Measurement Conditions ........ 143
Output Buffer Characteristics ................................. 144
Estimating Power Dissipation ................................. 146
Pin Information ....................................................... 149
Package Thermal Characteristics........................... 194
PCM Cautions ........................................................ 84
Initialization ............................................................. 85
Configuration .......................................................... 86
Start-Up .................................................................. 87
Reconfiguration ...................................................... 88
Partial Reconfiguration ........................................... 88
Other Configuration Options ................................... 88
Using ORCA Foundry to Generate
Configuration Data Frame ...................................... 89
Bit Stream Error Checking ...................................... 91
Master Parallel Mode ............................................. 92
Master Serial Mode ................................................ 93
Asynchronous Peripheral Mode ............................. 94
Microprocessor Interface (MPI) Mode .................... 94
Slave Serial Mode .................................................. 97
Slave Parallel Mode ............................................... 97
Daisy-Chaining ....................................................... 98
Daisy-Chaining with Boundary Scan ...................... 99
Recommended Operating Conditions .................. 100
Description ........................................................... 103
PFU Timing ......................................................... 104
PLC Timing ........................................................... 111
SLIC Timing .......................................................... 111
PIO Timing ........................................................... 112
Special Function Blocks Timing ........................... 115
Clock Timing ......................................................... 123
Configuration Timing ............................................ 133
Readback Timing ................................................. 142
OR3Cxx ................................................................ 144
OR3Txxx .............................................................. 145
OR3Cxx ................................................................ 146
OR3Txxx (Preliminary Information) ...................... 147
Pin Descriptions ................................................... 149
Package Compatibility .......................................... 153
Compatibility with OR2C/TxxA Series .................. 154
FPGA Maximum Junction Temperature ............... 195
Configuration RAM Data ....................................... 89
JC ...................................................................... 194
JA ....................................................................... 194
JC ...................................................................... 194
JB ...................................................................... 194
Lucent Technologies Inc.
Data Sheet
June 1999
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