OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 142

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OR3T125-5BA352

Manufacturer Part Number
OR3T125-5BA352
Description
3C and 3T Field-Programmable Gate Arrays
Manufacturer
AGERE [Agere Systems]
Datasheet
ORCA Series 3C and 3T FPGAs
Timing Characteristics
Readback Timing
Table 66 . Readback Timing Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
142
RD_CFG
RD_CFG
CCLK Low Time
CCLK High Time
CCLK Frequency
CCLK to RD_DATA Delay
RD_DATA
to CCLK Setup Time
High Width to Abort Readback
RD_CFG
CCLK
Parameter
DD
DD
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
S
(continued)
T
CH
Figure 88. Readback Timing Diagram
<
T
T
<
A
CL
<
T
BIT 0
A
70 °C; Industrial: V
T
Symbol
<
D
T
T
70 °C; Industrial: V
T
T
F
T
RBA
CH
CL
C
D
S
BIT 1
DD
50.00
40.00
40.00
DD
= 5.0 V ± 10%, –40 °C
Min
2
T
RBA
= 3.0 V to 3.6 V, –40 °C
12.50
40.00
Max
Lucent Technologies Inc.
<
T
A
<
<
T
+85 °C.
A
<
CCLK cycles
Data Sheet
BIT 0
June 1999
+85 °C.
Unit
MHz
ns
ns
ns
ns
5-4536(F)

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