OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 38

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
Inputs
As outlined earlier in Table 9, there are six major
options on the PIO inputs that can be selected in the
ORCA Foundry tools. For OR3Cxx devices, the inputs
and bidirectional buffers can be configured as either
TTL or CMOS compatible. OR3Txxx devices support
CMOS levels only for input or bidirectional buffers, have
5 V tolerant I/Os as previously explained, but can
optionally be selected on a pin-by-pin basis to be PCI
bus 3.3 V signaling compliant (PCI bus 5 V signaling
compliance occurs in 5 V tolerant operation). The
default buffer upon powerup for the unused sites is 5 V
tolerant/5 V PCI compliant. Consult the ORCA macro
library, Series 3 I/O cells, for the appropriate buffers.
Inputs may have a pull-up or pull-down resistor
selected on an input for signal stabilization and power
management. Input signals in a PIO can be passed to
PIC routing on any of three paths, two general signal
paths into PIC routing, and/or a fast route into the clock
routing system.
There is also a programmable delay available on the
input. When enabled, this delay affects the IN1 and IN2
signals of each PIO, but not the clock input. The delay
allows any signal to have a guaranteed zero hold time
when input. This feature is discussed subsequently.
Inputs should have transition times of less than 500 ns
and should not be left floating. If any pin is not used, it
is 3-stated with an internal pull-up resistor enabled
automatically after configuration.
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Warning: During configuration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5 V, they will draw substantial current
( 5 mA). This is due to the fact that the inputs are
pulled up to 3 V.
Floating inputs increase power consumption, produce
oscillations, and increase system noise. The OR3Cxx
inputs have a typical hysteresis of approximately 280
mV (200 mV for the OR3Txxx) to reduce sensitivity to
input noise. The PIC contains input circuitry which pro-
vides protection against latch-up and electrostatic dis-
charge.
The other features of the PIO inputs relate to the new
latch/FF structure in the input path. As shown in
Figure 23, the input is optionally passed to a register or
latch/register pair. These structures can operate in the
modes listed in Table 9. In latch mode, the input signal
is fed to a latch that is clocked by a system clock signal.
The clock may be inverted or noninverted from its
sense in the PIC routing. There is also a local set/reset
signal to the latch from the PIC routing. The senses of
these signals are also programmable as well as the
capability to enable or disable the global set/reset sig-
nal and select the set/reset priority. The same control
signals may also be used to control the input latch/FF
when it is configured as a FF instead of a latch, with the
addition of another control signal used as a clock
enable.
Lucent Technologies Inc.
Data Sheet
June 1999