OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 93

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
FPGA Configuration Modes
Master Serial Mode
In the master serial mode, the FPGA loads the configu-
ration data from an external serial ROM. The configura-
tion data is either loaded automatically at start-up or on
a
Series Serial PROMs can be used to configure the
FPGA in the master serial mode. This provides a sim-
ple 4-pin interface in a compact package.
Configuration in the master serial mode can be done at
powerup and/or upon a configure command. The sys-
tem or the FPGA must activate the serial ROM's
RESET
serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be configured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automati-
cally enters its initialization phase.
The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, avail-
ability of an intelligent host to generate a configure
command, whether a single serial ROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple configuration pro-
grams, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.
Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the CLK
input of the serial ROM. During the configuration pro-
cess, CCLK clocks one data bit on each rising edge.
Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the
ROM(s). There are several methods for enabling the
serial ROM’s
ROM’s
RESET active-high and
low and OE active-high.
In Figure 55, serial ROMs are cascaded to configure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's
FPGA’s
RESET
function with
The FPGA DONE is routed to the
DONE enables the serial ROMs. At the completion of
Lucent Technologies Inc.
PRGM
/OE and
/OE input, which has been programmed to
RESET
INIT
command to reconfigure. The ATT1700A
input is connected to the serial ROMs’
RESET
RESET
/OE is programmable to function with
CE
inputs. At powerup, the FPGA and
/OE and
RESET
active-low and OE active-high.
OE
/OE and
active-low or
CE
inputs. The serial
PRGM
CE
CE
pin. The low on
(continued)
of the serial
input. The
RESET
active-
configuration, the high on the FPGA's DONE disables
the serial ROM.
Serial ROMs can also be cascaded to support the con-
figuration of multiple FPGAs or to load a single FPGA
when configuration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the first serial ROM is read, the serial ROM outputs
CEO
ROM recognizes the low on
figuration data on the DATA output. After configuration
is complete, the FPGA’s DONE output into
the serial ROMs.
This FPGA/serial ROM interface is not used in applica-
tions in which a serial ROM stores multiple configura-
tion programs. In these applications, the next
configuration program to be loaded is stored at the
ROM location that follows the last address for the previ-
ous configuration program. The reason the interface in
Figure 55 will not work in this application is that the low
output on the
address pointer, causing the first configuration to be
reloaded.
In some applications, there can be contention on the
FPGA's DIN pin. During configuration, DIN receives
configuration data, and after configuration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in ORCA Foundry) may correct the problem.
An alternative is to use
CE
run the master serial configuration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
Figure 55. Master Serial Configuration Schematic
ATT1700A
ATT1700A
SERIAL ROMs
AS NEEDED
pin. In order to reduce noise, it is generally better to
TO MORE
low and 3-states the DATA output. The next serial
RESET/OE
RESET/OE
CEO
CEO
DATA
DATA
CLK
CLK
CE
CE
INIT
ORCA Series 3C and 3T FPGAs
signal would reset the serial ROM
PROGRAM
LDC
M2
M1
M0
CE
to drive the serial ROM's
DONE
INIT
PRGM
DIN
CCLK
input and outputs con-
SERIES
ORCA
FPGA
DOUT
CE
disables
TO DAISY-
CHAINED
DEVICES
5-4456.1(F)
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