OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 14

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
Table 4. Control Input Functionality
Logic Mode
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in flexible groups to implement user
logic functions. The latches/FFs may be used in con-
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of
LUT operation in PFU logic mode: F4 mode, F5 mode,
and softwired LUT (SWL) mode. Combinations of these
submodes are possible in each PFU.
F4 mode, shown simplified in Figure 4, illustrates the
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured
at the LUTs associated latch/FF, or multiplexed with the
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU. Only adjacent LUT pairs (K
and K
the output always goes to the even-numbered output of
the pair.
The F5 submode of the LUT operation, shown simpli-
fied in Figure 4, indicates the use of 5-input LUTs to
implement logic. 5-input LUTs are created from two
4-input LUTs and a multiplexer. The F5 LUT is the
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to the F4
LUTs be the same. The F5[A:D] input is then used as
the fifth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT. Any combination
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5
LUTs, and a combination of four F4 plus two F5 LUTs.
14
Half Ripple
Half Logic/
Memory
Memory
(ROM)
Ripple
(RAM)
Mode
Logic
3
, K
4
and K
CLK to all latches/
FFs
CLK to all latches/
FFs
CLK to all latches/
FFs
CLK to RAM
Optional for sync.
outputs
5
, K
CLK
6
and K
7
) can be multiplexed, and
LSR to all latches/
FFs, enabled per nib-
ble and for ninth FF
LSR to all latches/FF,
enabled per nibble
and for ninth FF
LSR to all latches/
FFs, enabled per nib-
ble and for ninth FF
Port enable 2
Not used
(continued)
LSR
0
and K
1
, K
2
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Port enable 1
Not used
CE
F4 MODE
Figure 4. Simplified F4 and F5 Logic Modes
K
K
K
K
K
K
K
K
7
6
5
4
3
2
1
0
F7
F6
F5
F4
F3
F2
F1
F0
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Ripple logic control
input
Ripple logic control
input
Write enable
Not used
MULTIPLEXED F4 MODE
F5D
F5C
F5B
F5A
K
K
K
K
K
K
K
K
ASWE
7
6
5
4
3
2
1
0
Lucent Technologies Inc.
F6
F4
F2
F0
Select between LUT
input and direct input
for eight latches/FFs
Select between LUT
input and direct input
for eight latches/FFs
Select between LUT
input and direct input
for eight latches/FFs
Not used
Not used
Data Sheet
F5 MODE
June 1999
K
K
K
K
SEL
7
5
3
1
/K
/K
/K
/K
6
4
2
0
F6
F4
F2
F0
5-5970(F)