OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 68

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
MPI
The MPI has a series of addressable registers that provide MPI control and status, configuration and readback data
transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The
address map for these registers and the user-logic address space are shown in Table 19, followed by descriptions
of the register and bit functions. Note that for all registers, the most significant bit is bit 7, and the least significant bit
is bit 0.
Table 19. MPI Setup and Control Registers
Control Register 1
The MPI control register 1 is a read/write register. The host processor writes a control byte to configure the MPI . It
is readable by the host processor to verify the status of control bits previously written.
Table 20. MPI Setup and Control Registers Descriptions
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Bit #
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Address
0B—0F
10—1F
Setup and Control
(Hex)
0A
00
01
02
03
04
05
06
07
08
09
GSR Input. Setting this bit to a 1 invokes a global set/reset on the FPGA. The host processor must
return this bit to a 0 to remove the GSR signal. GSR does not affect the registers at MPI addresses 0
through F hexadecimal or any configuration registers. Default state = 0.
Reserved.
Reserved.
Reserved.
Reserved.
RD_CFG
must return this bit to a 1 to remove the
input pin, please see the FPGA pin descriptions for more information on this signal. Default state = 1.
Reserved.
PRGM
scan circuitry. The host processor must return this bit to a 1 to remove the
works exactly like the
descriptions for more information on this signal. Default state = 1.
Input. Setting this bit to a 0 causes the FPGA to begin configuration and resets the boundary-
Control Register 1.
Control Register 2.
Scratchpad Register.
Status Register.
Configuration/Readback Data Register.
Readback Address Register 1 (bits [7:0]).
Readback Address Register 2 (bits [15:8]).
Device ID Register 1 (bits [7:0]).
Device ID Register 2 (bits [15:8]).
Device ID Register 3 (bits [23:16]).
Device ID Register 4 (bits [31:24]).
Reserved.
User-definable Address Space.
Input. Changing this bit to a 0 after configuration will initiate readback. The host processor
PRGM
input pin (except that it does not reset the MPI ), please see the FPGA pin
Register
(continued)
RD_CFG
Description
signal. Since this bit works exactly like the
PRGM
Lucent Technologies Inc.
signal. Since this bit
Data Sheet
June 1999
RD_CFG