S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 108

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

10.6
108
10.6.1
10.6.2
Erase Flash Array Commands
Sector Erase (SE D8h or 4SE DCh):
Bulk Erase (BE 60h or C7h):
The Sector Erase (SE) command sets all bits in the addressed sector to 1 (all bytes are FFh). Before the
Sector Erase (SE) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable
any write operations.
The instruction
 D8h [ExtAdd=0] is followed by a 3-byte address (A23-A0), or
 D8h [ExtAdd=1] is followed by a 4-byte address (A31-A0), or
 DCh is followed by a 4-byte address (A31-A0)
CS# must be driven into the logic high state after the twenty-fourth or thirty-second bit of address has been
latched in on SI. This will initiate the erase cycle, which involves the pre-programming and erase of the
chosen sector. If CS# is not driven high after the last bit of address, the sector erase operation will not be
executed.
As soon as CS# is driven into the logic high state, the internal erase cycle will be initiated. With the internal
erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the
operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a0 when
the erase cycle has been completed.
A Sector Erase (SE) command applied to a sector that has been Write Protected through the Block Protection
bits or ASP, will not be executed and will set the E_ERR status.
ASP has a PPB and a DYB protection bit for each sector.
The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array.
Before the BE command can be accepted by the device, a Write Enable (WREN) command must be issued
and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory
array. If CS# is not driven high after the last bit of instruction, the BE operation will not be executed.
As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in
progress, the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has
been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase
cycle has been completed.
A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0’s. If the BP
bits are not zero, the BE command is not executed and E_ERR is not set. The BE command will skip any
sectors protected by the DYB or PPB and the E_ERR status will not be set.
Phase
SCK
CS#
S O
S I
7
Figure 10.55 Sector Erase (SE D8h or 4SE DCh) Command Sequence
6
5
D a t a
Instruction
4
S25FL512S
S h e e t
3
2
( P r e l i m i n a r y )
1
0
A
S25FL512S_00_04 June 13, 2012
Address
1
0