S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 88

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

88
10.3.15
10.3.16
Write VDLR (WVDLR 4Ah)
Data Learning Pattern Read (DLPRD 41h)
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the
WVDLR command is not executed. As soon as CS# is driven to the logic high state, the WVDLR operation is
initiated with no delays. The maximum clock frequency for the PNVDLR command is 133 MHz.
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP
continuously by providing multiples of eight clock cycles. The maximum operating clock frequency for the
DLPRD command is 133 MHz.
Phase
SCK
CS#
SO
SI
Phase
SCK
CS#
SO
SI
Figure 10.22 DLP Read (DLPRD 41h) Command Sequence
7
6
5
Figure 10.21 Write VDLR (WVDLR 4Ah) Command Sequence
Instruction
7
4
6
3
D a t a
2
5
Instruction
1
4
S25FL512S
0
S h e e t
3
7
2
6
5
1
( P r e l i m i n a r y )
Data 1
4
0
3
7
2
6
1
0
5
Input Data
7
4
S25FL512S_00_04 June 13, 2012
6
3
5
Data N
2
4
3
1
2
0
1
0