S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 117

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

June 13, 2012 S25FL512S_00_04
10.8.11
10.8.12
Password Program (PASSP E8h)
Password Unlock (PASSU E9h)
the falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of
64 clock cycles. The maximum operating clock frequency for the PASSRD command is 133 MHz.
Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded, the device sets the Write Enable Latch (WEL) to enable the PASSP operation.
The password can only be programmed before the Password Mode is selected by programming the
Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is
selected the PASSP command is ignored.
The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64
PASSP command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSP
operation is initiated. While the PASSP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSP
cycle, and is a 0 when it is completed. The PASSP command can report a program error in the P_ERR bit of
the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The
maximum clock frequency for the PASSP command is 133 MHz.
The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the
password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is
sixty-four (64) bits in length.
CS# must be driven to the logic high state after the sixty-fourth (64
PASSU command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSU
operation is initiated. While the PASSU operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSU
cycle, and is a 0 when it is completed.
If the PASSU command supplied password does not match the hidden password in the Password Register,
an error is reported by setting the P_ERR bit to 1. The WIP bit of the status register also remains set to 1. It is
necessary to use the CLSR command to clear the status register, the RESET command to software reset the
Phase
Phase
SCK
CS#
SCK
CS#
SO
SO
SI
SI
Figure 10.71 Password Program (PASSP E8h) Command Sequence
D a t a
7
7
6
6
Figure 10.70 Password Read (PASSRD E7h) Command Sequence
5
Instruction
S h e e t
5
Instruction
4
4
3
3
2
2
( P r e l i m i n a r y )
1
1
0
S25FL512S
0
7
7
Input Password Low Byte
6
6
5
5
Data 1
4
4
3
3
2
2
1
1
th
th
) bit of data has been latched. If not, the
) bit of data has been latched. If not, the
0
0
7
7
6
Input Password High Byte
6
5
5
Data N
4
4
3
3
2
2
1
1
0
0
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