S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 72

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

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2. For backward compatibility to the 3-byte address instructions, the standard instructions can be
3. For backward compatibility to the 3-byte addressing, the standard instructions can be used in
used in conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7]
is cleared to 0 (following power up and hardware reset), to enable 3-byte (24-bit) addressing. When
set to 1, the legacy commands are changed to require 4 bytes (32 bits) for the address field. The
following instructions can be used in conjunction with EXTADD bit to switch from 3 bytes to 4 bytes
of address field.
conjunction with the Bank Address Register:
a. The Bank Address Register is used to switch between 128-Mbit (16-Mbyte) banks of memory,
b. The Bank Register provides the high order (4th) byte of address, which is used to address the
c. Bank Register bits are volatile.
d. For Read, the device will continuously transfer out data until the end of the array.
Bit 1
Bank Address Register Bits
0
0
1
1
The standard 3-byte address selects an address within the bank selected by the Bank Address
Register.
available memory at addresses greater than 16 Mbytes.
i. The host system writes the Bank Address Register to access beyond the first 128 Mbits of
memory.
ii. This applies to read, erase, and program commands.
i. There is no bank to bank delay.
ii. The Bank Address Register is not updated.
iii. The Bank Address Register value is used only for the initial address of an access.
i. On power up, the default is Bank0 (the lowest address 16 Mbytes).
Instruction Name
FAST_READ
DDRQIOR
DDRDIOR
DDRFR
READ
DIOR
QIOR
DOR
QOR
QPP
PP
SE
Bit 0
D a t a
0
1
0
1
Table 10.1 Bank Address Map
S25FL512S
S h e e t
DDR Quad I/O Read (3-byte Address)
Quad Page Program (3-byte Address)
DDR Dual I/O Read (3-byte Address)
Read Quad Out (3-byte Address)
Read DDR Fast (3-byte Address)
Quad I/O Read (3-byte Address)
Read Dual Out (3-byte Address)
Dual I/O Read (3-byte Address)
Page Program (3-byte Address)
Erase 256 kB (3-byte Address)
Read Fast (3-byte Address)
Read (3-byte Address)
Bank
Description
0
1
2
3
( P r e l i m i n a r y )
Memory Array Address Range (Hex)
00000000
01000000
02000000
03000000
S25FL512S_00_04 June 13, 2012
Code (Hex)
BB
EB
0D
BD
ED
D8
03
0B
3B
6B
02
32
00FFFFFF
01FFFFFF
02FFFFFF
03FFFFFF