S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 91

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

June 13, 2012 S25FL512S_00_04
10.4.2
10.4.3
Figure 10.25 Fast Read Command (FAST_READ 0Bh or 0Ch) Sequence without Read Latency
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch):
Dual Output Read (DOR 3Bh or 4DOR 3Ch):
Figure 10.24 Fast Read (FAST_READ 0Bh or 0Ch) Command Sequence with Read Latency
The instruction
 0Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 0Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 0Ch is followed by a 4-byte address (A31-A0)
The address is followed by zero or eight dummy cycles depending on the latency code set in the
Configuration Register. The dummy cycles allow the device internal circuits additional time for accessing the
initial address location. During the dummy cycles the data value on SO is “don’t care” and may be high
impedance. Then the memory contents, at the address given, are shifted out on SO.
The maximum operating clock frequency for FAST READ command is 133 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
The instruction
 3Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 3Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 3Ch is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1
(SO). Two bits are shifted out at the SCK frequency by the falling edge of the SCK signal.
The maximum operating clock frequency for the Dual Output Read command is 104 MHz. For Dual Output
Read commands, there are zero or eight dummy cycles required after the last address bit is shifted into SI
before data begins shifting out of IO0 and IO1. This latency period (i.e., dummy cycles) allows the device’s
internal circuitry enough time to read from the initial address. During the dummy cycles, the data value on SI
is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of
SCK (refer to
Phase
Phase
SCK
CS#
SCK
S O
CS#
S I
S O
S I
7
D a t a
7
Table 8.7, Latency Codes for SDR Enhanced High Performance on page
6
6
Instruction
5
Instruction
5
4 3
S h e e t
4 3
2
2
1 0 A
1 0 A
( P r e l i m i n a r y )
Address
Address
S25FL512S
1 0
1 0
7
Dummy Cycles
6 5
Data 1
4
3 2
1
0
7 6
7 6
5
5
Data 1
4 3
Data N
4
59).
3
2 1 0
2 1 0
91