S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 14

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

14
2.2.2.3
2.2.2.4
2.2.2.5
2.2.2.6
Configuration Register Freeze Bit
The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior
generations. In the FL-S family it also locks the state of the configuration register TBPARM bit CR1[2],
TBPROT bit CR1[5], and the Secure Silicon Region (OTP) area.
Sector Erase Commands
The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.
The command for erasing a 4-kbyte sector is not supported in the 512-Mbit density FL-S device.
The erase command for 64-kbyte sectors is not supported in the 512-Mbit density FL-S device.
Deep Power Down
The Deep Power Down (DPD) function is not supported in FL-S family devices.
The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can
issue the former DPD command, to access a new bank address register. The bank address register allows
SPI memory controllers that do not support more than 24 bits of address, the ability to provide higher order
address bits for commands, as needed to access the larger address space of the 256-Mbit density FL-S
device. For additional information see
New Features
The FL-S family introduces several new features to SPI category memories:
 Extended address for access to higher memory density.
 AutoBoot for simpler access to boot code following power up.
 Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO
 Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher
 DDR read commands for SIO, DIO, and QIO.
 Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to
instructions when repeating the same type of read command.
clock rate read commands.
the Advanced Sector Protection feature found in several other Spansion parallel interface NOR memory
families.
D a t a
Extended Address on page
S25FL512S
S h e e t
( P r e l i m i n a r y )
53.
S25FL512S_00_04 June 13, 2012