S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 93

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

June 13, 2012 S25FL512S_00_04
10.4.5
Figure 10.30 Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence without Read Latency
Figure 10.29 Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence with Read Latency
Dual I/O Read (DIOR BBh or 4DIOR BCh):
Then the memory contents, at the address given, is shifted out four bits at a time through IO0-IO3. Each
nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The maximum operating clock frequency for Quad Output Read command is 104 MHz. For Quad Output
Read Mode, there may be dummy cycles required after the last address bit is shifted into SI before data
begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry
enough time to set up for the initial address. During the dummy cycles, the data value on IO0-IO3 is a “don’t
care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK
(refer to
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
The QUAD bit of Configuration Register must be set (CR Bit1=1) to enable the Quad mode capability.
The instruction
 BBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 BBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar
to the Dual Output Read command but takes input of the address two bits per SCK rising edge. In some
applications, the reduced address input time might allow for code execution in place (XIP) i.e. directly from
the memory device.
The maximum operating clock frequency for Dual I/O Read is 104 MHz.
Phase
SCK
CS#
IO0
IO1
IO2
IO3
Table 8.7, Latency Codes for SDR Enhanced High Performance on page
D a t a
Phase
7
SCK
CS#
IO0
IO1
IO2
IO3
6
5
S h e e t
Instruction
7 6 5 4 3 2 1 0 A
4
Instruction
3
2
( P r e l i m i n a r y )
1
S25FL512S
Address
0
1 0
A
Address
Dummy
1
0
Data 1 Data 2 Data 3 Data 4 Data 5
4
5
6
7
0
1
2
3
4 0 4 0 4 0 4 0 4 0 4
5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6
7 3 7 3 7 3 7 3 7 3 7
D1 D2 D3 D4 D5
4
5
6
7
0
1
2
3
4
5
6
7
59).
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
...
4
5
6
7
93