S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 98

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

98
10.4.7
DDR Fast Read (DDRFR 0Dh, 4DDRFR 0Eh)
The instruction
 0Dh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 0Dh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 0Eh is followed by a 4-byte address (A31-A0)
The DDR Fast Read command improves throughput by transferring address and data on both the falling and
rising edge of SCK. It is similar to the Fast Read command but allows transfer of address and data on every
edge of the clock.
The maximum operating clock frequency for DDR Fast Read command is 66 MHz.
For the DDR Fast Read command, there is a latency required after the last address bits are shifted into SI
before data begins shifting out of SO. There are different ordering part numbers that select the latency code
table used for this command, either the High Performance LC (HPLC) table or the Enhanced High
Performance LC (EHPLC) table. The HPLC table does not provide cycles for mode bits so each DDR Fast
Read command starts with the 8 bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the
initial address. During the dummy cycles, the data value on SI is “don’t care” and may be high impedance.
The number of dummy cycles is determined by the frequency of SCK
Enhanced High Performance on page
Configuration Register (CR1).
Then the memory contents, at the address given, is shifted out, in DDR fashion, one bit at a time on each
clock edge through SO. Each bit is shifted out at the SCK frequency by the rising and falling edge of the SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
The EHPLC table does provide cycles for mode bits so a series of DDR Fast Read commands may eliminate
the 8 bit instruction after the first DDR Fast Read command sends a mode bit pattern of complementary first
and second Nibbles, e.g. A5h, 5Ah, 0Fh, etc., that indicates the following command will also be a DDR Fast
Read command. The first DDR Fast Read command in a series starts with the 8 bit instruction, followed by
address, followed by four cycles of mode bits, followed by a latency period. If the mode bit pattern is
complementary the next command is assumed to be an additional DDR Fast Read command that does not
provide instruction bits. That command starts with address, followed by mode bits, followed by latency.
When the EHPLC table is used, address jumps can be done without the need for additional DDR Fast Read
instructions. This is controlled through the setting of the Mode bits (after the address sequence, as shown in
Figure 10.39 on page 99
bit SDR instruction sequence to reduce initial access time (improves XIP performance). The Mode bits control
the length of the next DDR Fast Read operation through the inclusion or exclusion of the first byte instruction
code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and
Ah) then the next address can be entered (after CS# is raised high and then asserted low) without requiring
the 0Dh or 0Eh instruction, as shown in
Figure 10.38 Continuous Quad I/O Read Command Sequence (4-byte Address), LC=00b
Phase
SCK
CS#
IO0
IO1
IO2
IO3
4
5
6
7
DN-1
0
1
2
3
4
5
6
7
D N
0
1
2
3
and
Figure 10.41 on page
D a t a
28
29
30
31
Address
59). The number of dummy cycles is set by the LC bits in the
Figure 10.40
S25FL512S
S h e e t
4
5
6
7
0
1
2
3
Mode
4
5
6
7
100. This added feature removes the need for the eight
and
( P r e l i m i n a r y )
0
1
2
3
Figure
Dummy
10.42, thus, eliminating eight cycles from the
(Table 8.7, Latency Codes for SDR
4
5
6
7
D 1
S25FL512S_00_04 June 13, 2012
0
1
2
3
4
5
6
7
D 2
0
1
1
1
6
7
7
7
D 3
4
5
5
5
2
3
3
3
D 4
0
1
1
1