TRK-USB-MPC5643L Freescale Semiconductor, TRK-USB-MPC5643L Datasheet

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... Three 6-channel general-purpose eTimer units This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009–2012. All rights reserved. ® technology CPU • 2 FlexPWM units — ...

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... WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 110 3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 110 3.20.4 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.20.5 External interrupt timing (IRQ pin 115 3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 121 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 127 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

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... Instruction set PPC Instruction set VLE Instruction cache MPU-16 regions Semaphore unit (SEMA4) Buses Core bus Internal periphery bus Freescale Semiconductor Table 1. MPC5643L device summary MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction MPC5643L 2 × e200z4 (in lock-step or decoupled operation) Harvard 0–120 MHz (+2% FM) > ...

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... Module 4 × channels 2 × 12-bit ADC, 16 channels per ADC (3 internal, 4 shared and 9 external) 32 point 3 × DSPI as many as 8 chip selects Yes Yes, replicated module  16 3.0 V – 3.6 V and 4.5 V – 5 MHz 4 – 40 MHz Level 3+ Freescale Semiconductor ...

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... I/O access. 2 The second FlexPWM module is available only in the BGA package. 1.4 Block diagram Figure 1 shows a top-level block diagram of the MPC5643L device. Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction MPC5643L Yes 144 pins 257 MAPBGA ° ...

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... Redundancy Checker – Real Time Clock – Semaphore Unit – System Integration Unit Lite – System Status and Configuration Module – System Timer Module – Sine Wave Generator – Software Watchdog Timer – Temperature Sensor – Crystal Oscillator Freescale Semiconductor ...

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... The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers must be an instruction fetch from internal flash memory slave port is simultaneously requested by more than one master Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 ...

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... Each DMA task can optionally generate an interrupt at completion and retirement of the task • Signal to indicate closure of last minor loop • Transfer control descriptors mapped inside the SRAM The eDMA controller is replicated for each processing channel. 8 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

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... Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a least-recently-used replacement algorithm to maximize performance. • Programmable response for read-while-write sequences including support for stall-while-write, optional stall notification interrupt, optional flash operation abort, and optional abort notification interrupt. Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction 9 ...

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... SRAM 64-bit write (executed 32-bit writes) 0–2 SRAM 8-,16-bit write (Read-modify-Write for ECC) 0 Flash memory prefetch buffer hit (page hit) 3 Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle of program flash memory controller arbitration) MPC5643L Microcontroller Data Sheet, Rev. 8.1 Description Freescale Semiconductor ...

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... FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock (with max frequency 120 MHz) • On-chip crystal oscillator with automatic level control • Dedicated internal 16 MHz internal RC oscillator for rapid start-up Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction 11 ...

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... External reference clock (3.3 V) input mode • FMPLL reference 1.5.16 Internal Reference Clock (RC) oscillator The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap reference voltage. The RC oscillator is the device safe clock. 12 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

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... Safe internal RC oscillator as reference clock • Windowed watchdog • Program flow control monitor with 16-bit pseudorandom key generation • Allows a high level of safety (SIL3 monitor) The SWT module is replicated for each processor. 1.Automotive Open System Architecture Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction 1 requirement 13 ...

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... The SSCM on this device features the following: • System configuration and status • Debug port status and debug port enable • Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half Word 14 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

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... The FlexRay module provides the following features: • Full implementation of FlexRay Protocol Specification 2.1 Rev. A • 64 configurable message buffers can be handled • Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction 15 ...

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... Support for DMA enabled transfers 1.5.29 Deserial Serial Peripheral Interface (DSPI) The DSPI modules provide a synchronous serial interface for communication between the MPC5643L and external devices. A DSPI module provides these features: • Full duplex, synchronous transfers 16 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

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... Each complementary pair can operate with its own PWM frequency and deadtime values • Individual software control for each PWM output • All outputs can be forced to a value simultaneously • PWMX pin can optionally output a third signal from each channel Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction 17 ...

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... A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver). 1.5.33 Analog-to-Digital Converter module (ADC) The ADC module features include: Analog part: • 2 on-chip ADCs — 12-bit resolution SAR architecture — Same digital interface as in the MPC5604P family 18 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

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... ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling, independent result queue selection • DMA support with safety features 1.5.35 Cyclic Redundancy Checker (CRC) Unit The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register. Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction 19 ...

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... MDO (message data out) pins • 2 MSEO (message start/end out) pins • EVTO (event out) pin 1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package MPC5643L Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor ...

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... TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry 1.5.40 Voltage regulator / Power Management Unit (PMU) The on-chip voltage regulator module provides the following features: • Single external rail required Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction 21 ...

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... This device includes the following protection against latent faults: • Boot-time Memory Built-In Self-Test (MBIST) • Boot-time scan-based Logic Built-In Self-Test (LBIST) • Run-time ADC Built-In Self-Test (BIST) • Run-time Built-In Self Test of LVDs 22 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

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... RESET 32 D[8] 33 D[5] 34 D[6] 35 VSS_LV_PLL0_PLL1 36 VDD_LV_PLL0_PLL1 Figure 2. MPC5643L 144 LQFP pinout (top view) Figure 3 shows the MPC5643L in the 257 MAPBGA package. Freescale Semiconductor 144 LQFP package MPC5643L Microcontroller Data Sheet, Rev. 8.1 Package pinouts and signal descriptions A[4] 108 107 VPP_TEST F[12] 106 105 D[14] 104 G[3] ...

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... V NC TCK H[4] SS_LV DD_LV V V C[11] B[5] TMS DD_LV DD_LV NC C[12] A[ DD_LV_ SS_LV_ DD_HV B[14] G[10] G[8] COR COR _IO V SS_HV B[15] C[0] BCTRL A[1] D[11] _IO V DD_HV E[10] E[12] E[0] A[0] D[10] _IO V V DD_HV SS_HV E[11 G[11] _PMU _IO Freescale Semiconductor 17 V SS_HV _IO V SS_HV _IO F[12] G[3] I[3] G[4] G[6] H[6] H[15] A[3] B[4] H[5] G[5] G[7] G[9] V SS_HV _IO V SS_HV _IO 17 ...

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... D[1] 4 F[ DD_HV_IO 7 V SS_HV_IO 8 F[6] 9 MDO0 10 A[7] 11 C[4] 12 A[8] 13 C[5] Freescale Semiconductor Table 3. 144 LQFP pin function summary Peripheral Output function SIUL GPIO[6] DSPI_1 SIUL SIUL GPIO[49] eTimer_1 CTU_0 EXT_TGR FlexRay SIUL GPIO[84] NPC MDO[3] SIUL GPIO[85] NPC MDO[2] SIUL GPIO[86] NPC ...

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... GPIO[5] CS0 CS0 ETC[5] ETC[5] CS7 — — EIRQ[5] GPIO[39] A[1] A[1] — — SIN — — — GPIO[87] MCKO — GPIO[88] — — — GPIO[89] — GPIO[90] EVTO — GPIO[91] — EVTI GPIO[57] X[0] X[0] TXD — — — — — — Freescale Semiconductor ...

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... SS_LV_PLL0_PLL1 36 V DD_LV_PLL0_PLL1 37 D[7] 38 FCCU_F[ DD_LV_COR 40 V SS_LV_COR 41 C[1] 42 E[4] 43 B[7] 44 E[5] 45 C[2] 46 E[6] Freescale Semiconductor Peripheral Output function SIUL GPIO[56] DSPI_1 eTimer_1 DSPI_0 FlexPWM_0 SIUL GPIO[53] DSPI_0 FlexPWM_0 SIUL GPIO[54] DSPI_0 FlexPWM_0 FlexPWM_0 SIUL GPIO[55] DSPI_1 DSPI_0 SWG analog output FCCU SIUL ...

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... GPIO[71] — AN[6] — GPIO[66] — AN[5] — — — GPIO[25] — AN[11] — GPIO[26] — AN[12] — GPIO[27] — AN[13] — GPIO[28] — AN[14] — — — — — GPIO[29] — RXD — AN[0] — GPIO[73] — AN[7] — GPIO[31] — EIRQ[20] — AN[2] — GPIO[74] — AN[8] Freescale Semiconductor ...

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... C[0] 67 E[12] 68 E[0] 69 BCTRL 70 V DD_LV_COR 71 V SS_LV_COR 72 V DD_HV_PMU 73 A[0] 74 A[1] 75 G[11] 76 D[10] 77 G[10] Freescale Semiconductor Peripheral Output function SIUL eTimer_0 SIUL ADC_1 SIUL ADC_1 SIUL ADC_1 SIUL ADC_1 SIUL ADC_1 SIUL GPIO[0] eTimer_0 DSPI_2 SIUL SIUL GPIO[1] eTimer_0 DSPI_2 SIUL SIUL GPIO[107] FlexRay ...

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... EIRQ[29] GPIO[43] ETC[4] ETC[4] CS2 — GPIO[104] DBG0 — CS1 — — FAULT[0] — EIRQ[21] GPIO[44] ETC[5] ETC[5] CS3 — GPIO[103] B[3] B[3] GPIO[2] ETC[2] ETC[2] A[3] A[3] — SIN — ABS[0] — EIRQ[2] GPIO[101] X[3] X[3] CS3 — GPIO[21] — TDI — — Freescale Semiconductor ...

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... DD_LV_COR 94 V SS_LV_COR 95 V DD_HV_REG_1 96 V SS_HV_FLA 97 V DD_HV_FLA 98 G[6] 99 D[12] 100 G[4] 101 C[13] 102 G[2] 103 C[14] Freescale Semiconductor Peripheral Output function SIUL GPIO[20] JTAGC SIUL GPIO[3] eTimer_0 DSPI_2 FlexPWM_0 MC_RGM SIUL SIUL GPIO[102] FlexPWM_0 SIUL GPIO[60] FlexPWM_0 LINFlexD_1 SIUL GPIO[100] FlexPWM_0 eTimer_0 SIUL ...

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... GPIO[4] ETC[0] ETC[0] CS1 — ETC[4] ETC[4] — FAB — EIRQ[4] GPIO[16] TXD — ETC[2] ETC[2] — — EIRQ[15] GPIO[17] ETC[3] ETC[3] — — RXD — RXD — EIRQ[16] GPIO[42] CS2 — A[3] A[3] — FAULT[1] GPIO[93] ETC[4] ETC[4] — EIRQ[31] Freescale Semiconductor ...

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... Table 3. 144 LQFP pin function summary (continued) Pin # Port/function 113 F[15] 114 B[2] 115 F[14] 116 B[3] 117 E[13] 118 A[10] 119 E[14] 120 A[11] 121 E[15] Freescale Semiconductor Peripheral Output function SIUL GPIO[95] LINFlexD_1 SIUL GPIO[18] LINFlexD_0 SSCM DEBUG[2] SIUL SIUL GPIO[94] LINFlexD_1 SIUL GPIO[19] SSCM DEBUG[3] LINFlexD_0 SIUL ...

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... GPIO[12] SOUT — A[2] A[2] B[2] B[2] — EIRQ[11] — JCOMP GPIO[47] — ETC[0] ETC[0] A[1] A[1] — EXT_IN — EXT_SYNC GPIO[48] CA_TX — ETC[1] ETC[1] B[1] B[1] — — GPIO[51] CB_TX — ETC[4] ETC[4] A[3] A[3] GPIO[52] — ETC[5] ETC[5] B[3] B[3] — — — GPIO[80] A[1] A[1] — ETC[2] — EIRQ[28] Freescale Semiconductor ...

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... Pin # Port/function 134 A[9] 135 V DD_LV_COR 136 A[13] 137 V SS_LV_COR 138 B[6] 139 F[3] 140 D[2] 141 FCCU_F[1] 142 C[6] 143 A[14] Freescale Semiconductor Peripheral Output function SIUL GPIO[9] DSPI_2 FlexPWM_0 FlexPWM_0 SIUL GPIO[13] FlexPWM_0 DSPI_2 FlexPWM_0 SIUL SIUL GPIO[22] MC_CGM DSPI_2 SIUL SIUL GPIO[83] DSPI_0 SIUL GPIO[50] ...

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... RXD — RXD — EIRQ[14] Input function — — — GPIO[114] MDO[5] — GPIO[112] MDO[7] — GPIO[110] MDO[9] — GPIO[51] CB_TX — ETC[4] ETC[4] A[3] A[3] GPIO[47] — ETC[0] ETC[0] A[1] A[1] — EXT_IN — EXT_SYNC — GPIO[12] SOUT — A[2] A[2] B[2] B[2] — EIRQ[11] Freescale Semiconductor ...

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... A12 H[14] A13 A[10] A14 B[2] A15 C[10] A16 V SS_HV_IO_RING A17 V SS_HV_IO_RING B1 V SS_HV_IO_RING B2 V SS_HV_IO_RING B3 B[6] B4 A[14] B5 F[3] Freescale Semiconductor Peripheral Output function SIUL GPIO[122] FlexPWM_1 eTimer_2 SIUL GPIO[126] FlexPWM_1 eTimer_2 SIUL GPIO[10] DSPI_2 FlexPWM_0 FlexPWM_0 SIUL SIUL GPIO[18] LINFlexD_0 SSCM DEBUG[2] SIUL SIUL GPIO[42] DSPI_2 ...

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... ETC[5] ETC[5] B[3] B[3] GPIO[48] CA_TX — ETC[1] ETC[1] B[1] B[1] — GPIO[124] B[2] B[2] GPIO[79] CS1 — — EIRQ[27] GPIO[78] ETC[5] ETC[5] — EIRQ[26] GPIO[19] — — RXD GPIO[93] ETC[4] ETC[4] — EIRQ[31] GPIO[16] TXD — ETC[2] ETC[2] — — EIRQ[15] — — — Freescale Semiconductor ...

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... C5 D[2] C6 A[13 DD_HV_REG_2 C8 V DD_HV_REG_2 C9 I[0] C10 JCOMP C11 H[11] C12 I[1] C13 F[14] C14 B[1] C15 V SS_HV_IO_RING Freescale Semiconductor Peripheral Output function FCCU SIUL GPIO[50] eTimer_1 FlexPWM_0 FlexRay SIUL GPIO[13] FlexPWM_0 DSPI_2 FlexPWM_0 SIUL SIUL GPIO[128] eTimer_2 DSPI_0 FlexPWM_1 — SIUL GPIO[123] FlexPWM_1 SIUL GPIO[129] ...

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... FAB — EIRQ[4] GPIO[92] ETC[3] ETC[3] — EIRQ[30] GPIO[85] MDO[2] — GPIO[84] MDO[3] — GPIO[15] ETC[5] ETC[5] — RXD — RXD — EIRQ[14] GPIO[38] SOUT — B[1] B[1] — — EIRQ[24] — — GPIO[80] A[1] A[1] — ETC[2] — EIRQ[28] — — — Freescale Semiconductor ...

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... F[15] D14 V DD_HV_IO_RING D15 V PP_TEST D16 D[14] D17 G[3] E1 MDO0 E2 F[6] E3 D[1] E4 NMI E14 Not connected E15 C[14] E16 G[2] Freescale Semiconductor Peripheral Output function SIUL GPIO[11] DSPI_2 FlexPWM_0 FlexPWM_0 SIUL SIUL GPIO[77] eTimer_0 DSPI_2 SIUL SIUL GPIO[95] LINFlexD_1 1 SIUL GPIO[62] FlexPWM_0 eTimer_0 SIUL GPIO[99] FlexPWM_0 eTimer_0 ...

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... MDO[6] — GPIO[108] — GPIO[7] SOUT — — EIRQ[7] GPIO[8] — SIN — EIRQ[8] — — — — — — — — GPIO[45] ETC[1] ETC[1] — EXT_IN — EXT_SYNC GPIO[130] ETC[2] ETC[2] CS6 — — FAULT[2] GPIO[100] B[2] B[2] — ETC[5] Freescale Semiconductor ...

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... G9 V SS_LV_CORE_RING G10 V SS_LV_CORE_RING G11 V SS_LV_CORE_RING G12 V DD_LV_CORE_RING G14 D[12] G15 H[13] G16 H[9] G17 G[6] H1 G[13 SS_HV_IO_RING Freescale Semiconductor Peripheral Output function SIUL GPIO[115] NPC MDO[4] SIUL GPIO[37] DSPI_0 SSCM DEBUG[5] FlexPWM_0 SIUL SIUL GPIO[6] DSPI_1 SIUL SIUL GPIO[60] FlexPWM_0 LINFlexD_1 SIUL GPIO[125] FlexPWM_1 ...

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... EIRQ[22] GPIO[5] CS0 CS0 ETC[5] ETC[5] CS7 — — EIRQ[5] — — — — — — — — — — GPIO[118] B[0] B[0] CS5 — GPIO[87] MCKO — GPIO[111] MDO[8] — — — — — — — — — Freescale Semiconductor ...

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... SS_LV K8 V SS_LV K9 V SS_LV K10 V SS_LV K11 V SS_LV K12 V DD_LV K14 Not connected K15 H[8] K16 H[7] Freescale Semiconductor Peripheral Output function SIUL GPIO[127] FlexPWM_1 eTimer_2 SIUL GPIO[89] NPC MSEO[0] SIUL GPIO[88] NPC MSEO[1] NPC SIUL GPIO[132] SIUL GPIO[39] FlexPWM_0 SSCM DEBUG[7] ...

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... ABS[2] — EIRQ[3] GPIO[90] EVTO — GPIO[91] — EVTI GPIO[57] X[0] X[0] TXD — — — — — — — — — — — GPIO[116] X[0] X[0] ETC[0] ETC[0] GPIO[20] TDO — — — GPIO[56] CS2 — ETC[4] ETC[4] CS5 — — FAULT[3] Freescale Semiconductor ...

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... M14 C[11] M15 B[5] M16 TMS M17 H[5] N1 XTAL N2 V SS_HV_IO_RING N3 D[ SS_LV_PLL0_PLL1 N14 Not connected N15 C[12] N16 A[2] Freescale Semiconductor Peripheral Output function SIUL GPIO[43] eTimer_0 DSPI_2 SIUL GPIO[21] JTAGC SIUL GPIO[117] FlexPWM_1 DSPI_0 SIUL GPIO[53] DSPI_0 FlexPWM_0 SIUL GPIO[44] eTimer_0 DSPI_2 SIUL GPIO[2] ...

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... FAULT[1] — — — — GPIO[24] — ETC[5] — AN[1] — — — — GPIO[30] — ETC[4] — EIRQ[19] — AN[1] — — — GPIO[106] DBG2 — CS3 — — FAULT[2] GPIO[104] DBG0 — CS1 — — FAULT[0] — EIRQ[21] Freescale Semiconductor ...

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... B[ DD_HV_ADR0 R8 B[10 DD_HV_ADR1 R10 B[13] R11 B[15] R12 C[0] R13 BCTRL R14 A[1] R15 V SS_HV_IO_RING Freescale Semiconductor Peripheral Output function SIUL GPIO[103] FlexPWM_0 FCCU SIUL GPIO[55] DSPI_1 DSPI_0 SWG analog output SIUL LINFlexD_0 ADC_0 SIUL ADC_0 SIUL ADC_0 ADC_1 SIUL LINFlexD_1 ADC_1 SIUL ...

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... FAULT[1] — EIRQ[29] — — — — GPIO[33] — AN[2] — GPIO[69] — AN[8] — GPIO[71] — AN[6] — — GPIO[27] — AN[13] — — GPIO[73] — AN[7] — GPIO[74] — AN[8] — GPIO[76] — AN[6] — GPIO[64] — AN[5] GPIO[0] ETC[0] ETC[0] SCK SCK — EIRQ[0] Freescale Semiconductor ...

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... U12 Not connected U13 Not connected U14 V DD_HV_PMU U15 G[11] U16 V SS_HV_IO_RING U17 V SS_HV_IO_RING 1 V should always be tied to ground (V PP_TEST Freescale Semiconductor Peripheral Output function SIUL GPIO[58] FlexPWM_0 eTimer_0 SIUL ADC_0 SIUL ADC_0 SIUL ADC_0 SIUL ADC_0 ADC_1 SIUL ADC_0 ADC_1 SIUL ...

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... R13 1 70 VDD_LV 2 71 VSS_LV 72 U14 U10 3 6 VDD_HV 4 7 VSS_HV VDD_HV 4 22 VSS_HV VSS_HV 3 91 VDD_HV 95 H15 96 J16 97 H16 3 126 VDD_HV 4 127 VSS_HV 130 VSS_HV Freescale Semiconductor ...

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Table 5. Supply pins (continued) Supply Symbol Description V VDD_LV_COR DD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest V V 1V2 VSS_LV_PLL0_PLL1 / SS 1.2 V Decoupling pins for on-chip FMPLL ...

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Table 5. Supply pins (continued) Symbol V 1V2 VDD_LV_COR DD Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest V V 1V2 VSS_LV_COR SS Decoupling pins for core logic. Decoupling capacitor must be ...

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Symbol 2 TCK JTAG clock 5 JCOMP JTAG compliance select RESET Bidirectional reset with Schmitt-Trigger characteristics and noise filter. This pin has medium drive strength. Output drive is open drain and must be terminated by an external resistor of value ...

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Alternate Port PCR Peripheral output name function A[0] PCR[0] SIUL GPIO[0] eTimer_0 ETC[0] DSPI_2 SCK SIUL — A[1] PCR[1] SIUL GPIO[1] eTimer_0 ETC[1] DSPI_2 SOUT SIUL — A[2] PCR[2] SIUL GPIO[2] eTimer_0 ETC[2] FlexPWM_0 A[3] DSPI_2 — MC_RGM — SIUL ...

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Alternate Port PCR Peripheral output name function A[3] PCR[3] SIUL GPIO[3] eTimer_0 ETC[3] DSPI_2 CS0 FlexPWM_0 B[3] MC_RGM — SIUL — A[4] PCR[4] SIUL GPIO[4] eTimer_1 ETC[0] DSPI_2 CS1 eTimer_0 ETC[4] MC_RGM — SIUL — A[5] PCR[5] SIUL GPIO[5] DSPI_1 ...

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Alternate Port PCR Peripheral output name function A[7] PCR[7] SIUL GPIO[7] DSPI_1 SOUT SIUL — A[8] PCR[8] SIUL GPIO[8] DSPI_1 — SIUL — A[9] PCR[9] SIUL GPIO[9] DSPI_2 CS1 FlexPWM_0 B[3] FlexPWM_0 — A[10] PCR[10] SIUL GPIO[10] DSPI_2 CS0 FlexPWM_0 ...

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Alternate Port PCR Peripheral output name function A[12] PCR[12] SIUL GPIO[12] DSPI_2 SOUT FlexPWM_0 A[2] FlexPWM_0 B[2] SIUL — A[13] PCR[13] SIUL GPIO[13] FlexPWM_0 B[2] DSPI_2 — FlexPWM_0 — SIUL — A[14] PCR[14] SIUL GPIO[14] FlexCAN_1 TXD eTimer_1 ETC[4] SIUL ...

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Alternate Port PCR Peripheral output name function B[0] PCR[16] SIUL GPIO[16] FlexCAN_0 TXD eTimer_1 ETC[2] SSCM DEBUG[0] SIUL — B[1] PCR[17] SIUL GPIO[17] eTimer_1 ETC[3] SSCM DEBUG[1] FlexCAN_0 — FlexCAN_1 — SIUL — B[2] PCR[18] SIUL GPIO[18] LINFlexD_0 TXD SSCM ...

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Alternate Port PCR Peripheral output name function B[5] PCR[21] SIUL GPIO[21] JTAGC — B[6] PCR[22] SIUL GPIO[22] MC_CGM clk_out DSPI_2 CS2 SIUL — B[7] PCR[23] SIUL — LINFlexD_0 — ADC_0 — B[8] PCR[24] SIUL — eTimer_0 — ADC_0 — B[9] ...

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Alternate Port PCR Peripheral output name function B[13] PCR[29] SIUL — LINFlexD_1 — ADC_1 — B[14] PCR[30] SIUL — eTimer_0 — SIUL — ADC_1 — B[15] PCR[31] SIUL — SIUL — ADC_1 — C[0] PCR[32] SIUL — ADC_1 — C[1] ...

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Alternate Port PCR Peripheral output name function C[5] PCR[37] SIUL GPIO[37] DSPI_0 SCK SSCM DEBUG[5] FlexPWM_0 — SIUL — C[6] PCR[38] SIUL GPIO[38] DSPI_0 SOUT FlexPWM_0 B[1] SSCM DEBUG[6] SIUL — C[7] PCR[39] SIUL GPIO[39] FlexPWM_0 A[1] SSCM DEBUG[7] DSPI_0 ...

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Alternate Port PCR Peripheral output name function C[12] PCR[44] SIUL GPIO[44] eTimer_0 ETC[5] DSPI_2 CS3 C[13] PCR[45] SIUL GPIO[45] eTimer_1 ETC[1] CTU_0 — FlexPWM_0 — C[14] PCR[46] SIUL GPIO[46] eTimer_1 ETC[2] CTU_0 EXT_TGR C[15] PCR[47] SIUL GPIO[47] FlexRay CA_TR_EN eTimer_1 ...

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Alternate Port PCR Peripheral output name function D[0] PCR[48] SIUL GPIO[48] FlexRay CA_TX eTimer_1 ETC[1] FlexPWM_0 B[1] D[1] PCR[49] SIUL GPIO[49] eTimer_1 ETC[2] CTU_0 EXT_TGR FlexRay — D[2] PCR[50] SIUL GPIO[50] eTimer_1 ETC[3] FlexPWM_0 X[3] FlexRay — D[3] PCR[51] SIUL ...

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Alternate Port PCR Peripheral output name function D[4] PCR[52] SIUL GPIO[52] FlexRay CB_TR_EN eTimer_1 ETC[5] FlexPWM_0 B[3] D[5] PCR[53] SIUL GPIO[53] DSPI_0 CS3 FlexPWM_0 — D[6] PCR[54] SIUL GPIO[54] DSPI_0 CS2 FlexPWM_0 X[3] FlexPWM_0 — D[7] PCR[55] SIUL GPIO[55] DSPI_1 ...

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Alternate Port PCR Peripheral output name function D[9] PCR[57] SIUL GPIO[57] FlexPWM_0 X[0] LINFlexD_1 TXD D[10] PCR[58] SIUL GPIO[58] FlexPWM_0 A[0] eTimer_0 — D[11] PCR[59] SIUL GPIO[59] FlexPWM_0 B[0] eTimer_0 — D[12] PCR[60] SIUL GPIO[60] FlexPWM_0 X[1] LINFlexD_1 — D[14] ...

Page 68

Alternate Port PCR Peripheral output name function E[4] PCR[68] SIUL — ADC_0 — E[5] PCR[69] SIUL — ADC_0 — E[6] PCR[70] SIUL — ADC_0 — E[7] PCR[71] SIUL — ADC_0 — E[9] PCR[73] SIUL — ADC_1 — E[10] PCR[74] SIUL ...

Page 69

Alternate Port PCR Peripheral output name function E[15] PCR[79] SIUL GPIO[79] DSPI_0 CS1 SIUL — F[0] PCR[80] SIUL GPIO[80] FlexPWM_0 A[1] eTimer_0 — SIUL — F[3] PCR[83] SIUL GPIO[83] DSPI_0 CS6 F[4] PCR[84] SIUL GPIO[84] NPC MDO[3] F[5] PCR[85] SIUL ...

Page 70

Alternate Port PCR Peripheral output name function F[11] PCR[91] SIUL GPIO[91] NPC — F[12] PCR[92] SIUL GPIO[92] eTimer_1 ETC[3] SIUL — F[13] PCR[93] SIUL GPIO[93] eTimer_1 ETC[4] SIUL — F[14] PCR[94] SIUL GPIO[94] LINFlexD_1 TXD F[15] PCR[95] SIUL GPIO[95] LINFlexD_1 ...

Page 71

Alternate Port PCR Peripheral output name function G[3] PCR[99] SIUL GPIO[99] FlexPWM_0 A[2] eTimer_0 — G[4] PCR[100] SIUL GPIO[100] FlexPWM_0 B[2] eTimer_0 — G[5] PCR[101] SIUL GPIO[101] FlexPWM_0 X[3] DSPI_2 CS3 G[6] PCR[102] SIUL GPIO[102] FlexPWM_0 A[3] G[7] PCR[103] SIUL ...

Page 72

Alternate Port PCR Peripheral output name function G[9] PCR[105] SIUL GPIO[105] FlexRay DBG1 DSPI_1 CS1 FlexPWM_0 — SIUL — G[10] PCR[106] SIUL GPIO[106] FlexRay DBG2 DSPI_2 CS3 FlexPWM_0 — G[11] PCR[107] SIUL GPIO[107] FlexRay DBG3 FlexPWM_0 — G[12] PCR[108] SIUL ...

Page 73

Alternate Port PCR Peripheral output name function H[1] PCR[113] SIUL GPIO[113] NPC MDO[6] H[2] PCR[114] SIUL GPIO[114] NPC MDO[5] H[3] PCR[115] SIUL GPIO[115] NPC MDO[4] H[4] PCR[116] SIUL GPIO[116] FlexPWM_1 X[0] eTimer_2 ETC[0] H[5] PCR[117] SIUL GPIO[117] FlexPWM_1 A[0] DSPI_0 ...

Page 74

Alternate Port PCR Peripheral output name function H[10] PCR[122] SIUL GPIO[122] FlexPWM_1 X[2] eTimer_2 ETC[2] H[11] PCR[123] SIUL GPIO[123] FlexPWM_1 A[2] H[12] PCR[124] SIUL GPIO[124] FlexPWM_1 B[2] H[13] PCR[125] SIUL GPIO[125] FlexPWM_1 X[3] eTimer_2 ETC[3] H[14] PCR[126] SIUL GPIO[126] FlexPWM_1 ...

Page 75

... Symmetric (for FlexRay) 2 The default function of this pin out of reset is ALT1 (TDO). 3 Analog Open Drain can be configured by the PCRn for all pins used as output (except FCCU_F[0] and FCCU_F[1] ). Freescale Semiconductor Table 7. Pin muxing (continued) Alternate Output Input output mux sel functions ...

Page 76

... MPC5643L Microcontroller Data Sheet, Rev. 8 Min Max 3, 4 — –0.3 4 — –0.3 4.0 — –0.1 0 — –0.3 4.0 — –0.1 0 — –0.3 4.0 — –0.1 0.1 — –0.3 6.0 — –0.1 0 — –0.3 4.0 — –0.1 0.1 Freescale Semiconductor Unit ...

Page 77

... SR ADC_0 ground and low reference voltage SS_HV_AD0 V ADC_1 ground and low reference voltage SS_HV_AD1 V SR 3.3 V ADC supply ground SS_HV_ADV Freescale Semiconductor Parameter Conditions ) Relative to V cannot be operated be operated at different voltages, and need to be supplied by the Parameter MPC5643L Microcontroller Data Sheet, Rev. 8.1 ...

Page 78

... MHz f –40 125 CPU — –40 150 ) must be shorted to high voltage grounds 1 Conditions Value Unit 46 °C °C/W 28 — 19 °C/W — 8 °C/W — 2 °C/W Freescale Semiconductor Unit °C °C ...

Page 79

... Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Freescale Semiconductor Parameter Single layer board – 1s Four layer board – 2s2p Single layer board – ...

Page 80

... Equation ×  C/W) Equation JA JC CA Equation ( × MPC5643L Microcontroller Data Sheet, Rev. 8 the sum of a junction to case thermal resistance Freescale Semiconductor Eqn. 1 Eqn. 2 Eqn. 3 ...

Page 81

... Reference emission = pads use min, mid and max slew rates, LVDS pads disabled • Oscillator frequency = 40 MHz • System bus frequency = 80 MHz • 2% PLL frequency modulation • IEC level K( 30 dBV) Freescale Semiconductor Table 14 is explained in Table Table 13. EMI configuration summary Description MPC5643L Microcontroller Data Sheet, Rev ...

Page 82

... AEC-Q100-011 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Min Typ Max Unit — 16 — dBV — 16 — — 32 — — 25 — — 15 — — 21 — — 30 — — 24 — 3 Class Max value Unit H1C 2000 V M2 200 V C3A 500 V 750 (corners) Freescale Semiconductor ...

Page 83

... D T =25° Maximum peak collector current CMaxDC VCE Collector-to-emitter saturation SAT voltage(Max) V Base-to-emitter voltage (Max) BE Freescale Semiconductor Table 16. Latch-up results Parameter T = 125 °C conforming to JESD 78 A DDIO ) DDREG DDFLASH Parameter 1 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Electrical characteristics Conditions ...

Page 84

... MPC5643L Microcontroller Data Sheet, Rev. 8.1 SAT Min Typ Max 12 — 40 0.01 — 0.10 5 — — 300 — 900 — — 2.5 — — 2.9 2.6 — — 1.355 — 1.495 1.39 — 1.47 1.315 — 1.455 1.35 — 1.38 Freescale Semiconductor Unit µF  — ...

Page 85

... RC filter at LVD input — D HVD_DIG: Time constant of RC filter at LVD input — D LVD_DIG: Time constant of RC filter at LVD input Freescale Semiconductor Conditions Before a destructive reset initialization phase completion After a destructive reset initialization phase completion — — 3.3V noise rejection at the ...

Page 86

... MPC5643L Microcontroller Data Sheet, Rev. 8.1 V1V2 ring on board ESR C v1v2 C ext V1V2 pin < 3.6 V). 1 Min Typ Max 2 –0.1 — — — — 0.35 V DD_HV_IOx — — DD_HV_IOx — — V DD_HV_IOx — — DD_HV_IOx — — 0.5 Freescale Semiconductor Unit 0 ...

Page 87

... D RESET, equivalent pull-down current PD 1 These specifications are design targets and subject to change per device characterization. 2 “SR” parameter values must not exceed the absolute maximum ratings shown in 3.10 Supply current characteristics Current consumption data is given in characterization. Freescale Semiconductor Conditions I = –1 DD_HV_IOx – ...

Page 88

... CPU — — 41 mA+ 2.30 mA*f [MHz] CPU — — 279 mA — — 318 mA — — 250 — — 290 — — 275 — — 299 — — 189 — — 214 — — 253 Freescale Semiconductor Unit ...

Page 89

... Internal structures hold the input voltage less than VDDA + 1 all pads powered by VDDA supplies, if the maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications. 4 This value is the total current for both ADCs. 5 VFLASH is only available in the calibration package. Freescale Semiconductor 1 Conditions T = ambient ...

Page 90

... Conditions T = –40 °C to 150 °C J Figure 5 describes a simple model of the internal oscillator driver and EXTAL DEVICE XTAL DEVICE NOTE MPC5643L Microcontroller Data Sheet, Rev. 8.1 Min Max Unit –10 10 °C — 4 — µs EXTAL XTAL C L EXTAL XTAL Freescale Semiconductor ...

Page 91

... SR Input low level CMOS IL Schmitt Trigger 3.3 V ±10 –40 to +150 °C, unless otherwise specified The recommended configuration for maximizing the oscillator margin are: XOSC_MARGIN = 0 for 4 MHz quartz XOSC_MARGIN = 1 for 8/16/40 MHz quartz Freescale Semiconductor 90% 10% T valid internal clock XOSCHSSU 1 Conditions — 3.3 V ±10 ...

Page 92

... FMPLLOUT –18 — FMPLLOUT ±0.25 — ±2 FMPLLOUT –0.5 — -8.0 — — 100 kHz Freescale Semiconductor ...

Page 93

... Table 24. RC oscillator electrical characteristics Symbol Parameter oscillator frequency RC 3.15 ADC electrical characteristics The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter. Freescale Semiconductor and V and variation in crystal oscillator frequency increase the DDPLL SSPLL Conditions — MPC5643L Microcontroller Data Sheet, Rev. 8.1 Electrical characteristics ...

Page 94

... V (LSB ) in(A) ideal equal to 7.5 pF, a resistance of 133 k is obtained S ) and the sum   -------------------- - LSB MPC5643L Microcontroller Data Sheet, Rev. 8.1 Offset Error OSE Gain Error GE being the external circuit must Freescale Semiconductor Eqn. 4 ...

Page 95

... Figure 9. Transient Behavior during Sampling Phase In particular two different transient periods can be distinguished: • A first and quick charge transfer from the internal capacitance C is supposed initially completely discharged): considering a worst case (since the time constant in reality would be Freescale Semiconductor Filter Current Limiter R R ...

Page 96

... and C , then the final voltage Equation 10 must be respected (charge A1   filter, is not able the time constant R A Freescale Semiconductor are in series, Eqn Eqn. 6 Eqn. 7 Eqn. 8 Eqn. 9 (source A2 Eqn ...

Page 97

... The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop from the two charge balance equations above simple to derive S voltage From this formula, in the worst case (when V half a count, a constraint is evident on C Freescale Semiconductor ) A  (Conversion Rate vs. Filter Pole  ...

Page 98

... Vref = 3.3V 67 — Vref = 5.0V 69 — — -65 — — 65 — — 10.5 — –6 — –8 — –8 — –10 — AGND AREF Freescale Semiconductor Unit MHz KHz 3 — ns — ( k   3 LSB 2 LSB 6 LSB 6 LSB — ...

Page 99

... These values are characterized, but not tested. 4 Program times are actual hardware programming times and do not include software overhead. 5 Program times are actual hardware programming times and do not include software overhead. Freescale Semiconductor , but only the time for determining the digital result and the time to sample Parameter 4 5 MPC5643L Microcontroller Data Sheet, Rev ...

Page 100

... MPC5643L Microcontroller Data Sheet, Rev. 8.1 Value Unit Min Typ Max — — 100 — — 5 100 — — 10 Value Minimu Typical Maximum m 100000 — — 1000 100000 — — — 10 — — 5 — — Freescale Semiconductor ns ns  Unit cycles cycles years ...

Page 101

... AC specifications 3.18.1 Pad AC specifications Table 30. Pad AC specifications (3 IPP_HVE = 0 ) Tswitchon (ns) No. Pad Min Typ 1 Slow Medium Freescale Semiconductor Table 29. MPC5643L SWG Specifications Minimum 12 MHz 1kHz 1 0 -6% 3 — -   230 1 2 Rise/Fall Frequency (ns) ...

Page 102

... Figure 11. Pad output delay MPC5643L Microcontroller Data Sheet, Rev. 8.1 1 (continued) 3 Current slew Load drive (MHz) (mA/ns) Typ Max Min Typ Max — — 40 — — 40 — — 40 — — 40 — — DDE Freescale Semiconductor (pF 100 200 25 ...

Page 103

... RESET asserted low beyond the last PHASE3. Reset Sequence Trigger Reset Sequence Start Condition PHASE0 PHASE1,2 Establish IRC Flash init and PWR Figure 12. Destructive Reset Sequence, BIST enabled Freescale Semiconductor Table 31. RESET sequences Parameter NOTE RESET RESET_B PHASE3 BIST Device ...

Page 104

... RESET PHASE1,2 PHASE3 Device Flash init Config T < T < T FRL, min Reset FRL, max Figure 15. Functional Reset Sequence Long MPC5643L Microcontroller Data Sheet, Rev. 8.1 DRUN Application Execution PHASE1,2 PHASE3 DRUN Device Application Flash init Config Execution DRUN Application Execution Freescale Semiconductor ...

Page 105

... The following table shows the possible trigger events for the different reset sequences. It specifies the reset sequence start conditions as well as the reset sequence end indications that are the basis for the timing data provided in 1.See RGM_FBRE register for more details. Freescale Semiconductor Reset Sequence Trigger Reset Sequence Start Condition ...

Page 106

... MPC5643L Microcontroller Data Sheet, Rev. 8.1 Reset Sequence External Functiona Functiona Reset l Reset l Reset Sequenc Sequenc Sequenc e Long, e Long e Short 1 BIST enabled cannot cannot cannot trigger trigger trigger 4 5 triggers triggers triggers cannot triggers cannot trigger trigger cannot cannot triggers trigger trigger Freescale Semiconductor 6 ...

Page 107

... Destructive Reset Sequence, BIST disabled. V Figure 17. Reset sequence start for Destructive Resets 3.19.4.2 External reset via RESET Figure 18 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of RESET as specified in Table 32. Freescale Semiconductor V max V min T starts here Reset, max T starts here Reset, min Table 33 ...

Page 108

... Basic Application Init Application Running Basic Application Init T Reset, max Earliest Latest Application Application Start Start MPC5643L Microcontroller Data Sheet, Rev. 8.1 t Section 3.19, Reset sequence can be used Figure 19 shows the relationships between Watchdog trigger Application Running Application time required to prepare watchdog trigger Freescale Semiconductor ...

Page 109

... RESET V RESET filtered by filtered by lowpass filter hysteresis W Freescale Semiconductor device start-up phase Figure 20. Start-up reset requirements unknown reset filtered by state lowpass filter W FRST FRST W NFRST Figure 21. Noise filtering on reset signal MPC5643L Microcontroller Data Sheet, Rev. 8.1 ...

Page 110

... Conditions Min Max Unit — 62.5 — — — — 3 — 5 — — 25 — — — 20 — 0 — — — 20 — — 50 — — 50 — — 50 — 50 — — 50 — Freescale Semiconductor Unit ...

Page 111

... TCK 3 TCK TMS, TDI TDO Freescale Semiconductor 1 Figure 22. JTAG test clock input timing Figure 23. JTAG test access port timing MPC5643L Microcontroller Data Sheet, Rev. 8.1 Electrical characteristics 111 ...

Page 112

... Figure 24. JTAG boundary scan timing Table 37. Nexus debug port timing Parameter 3 MPC5643L Microcontroller Data Sheet, Rev. 8 Conditions Min Max — 15.6 — — — –0.1 0.25 t — 4.0 — — 1 — 62.5 — — — 8 — 5 — Freescale Semiconductor Unit ns % MCYC t TCYC t MCYC ...

Page 113

... The system clock frequency needs to be four times faster than the TCK frequency. MCKO MDO MSEO EVTO EVTI Freescale Semiconductor Output Data Valid Figure 25. Nexus output timing 4 Figure 26. Nexus EVTI Input Pulse Width MPC5643L Microcontroller Data Sheet, Rev. 8.1 Electrical characteristics ...

Page 114

... Electrical characteristics MCKO MDO, MSEO MDO/MSEO data are valid during MCKO rising and falling edge Figure 27. Nexus Double Data Rate (DDR) Mode output timing 114 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

Page 115

... IPWH IRQ edge to edge time ICYC 1 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. Freescale Semiconductor 9 Figure 28. Nexus TDI, TMS, TDO timing Table 38. External interrupt timing Parameter 1 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Electrical characteristics ...

Page 116

... MPC5643L Microcontroller Data Sheet, Rev. 8.1 Min Max 62 — 62 — — 16 — 16 — SCK SCK — 40 — — 13 — 20 — 2 — 5 — 20 — –5 — 4 — 11 — –5 — — 4 — 23 — 12 — 4 Freescale Semiconductor Unit ...

Page 117

... SIN, but no valid data is transmitted on SOUT. PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Note: The numbers shown are referenced in Figure 30. DSPI classic SPI timing — master, CPHA = 0 Freescale Semiconductor Table 39. DSPI timing (continued) Conditions Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = ...

Page 118

... Figure 32. DSPI classic SPI timing — slave, CPHA = 0 118 9 Data First Data 12 Data First Data Table 39 First Data Data Last Data 9 10 First Data Data Last Data Table 39. MPC5643L Microcontroller Data Sheet, Rev. 8.1 10 Last Data 11 Last Data Freescale Semiconductor ...

Page 119

... Figure 33. DSPI classic SPI timing — slave, CPHA = 1 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Note: The numbers shown are referenced in Figure 34. DSPI modified transfer format timing — master, CPHA = 0 Freescale Semiconductor 11 5 Data First Data 9 10 Data First Data Table 39 ...

Page 120

... Figure 36. DSPI modified transfer format timing – slave, CPHA = 0 120 9 First Data Data 12 First Data Data Table 39 First Data Data Last Data 10 9 Data Last Data First Data Table 39. MPC5643L Microcontroller Data Sheet, Rev. 8.1 10 Last Data 11 Last Data Freescale Semiconductor ...

Page 121

... SIN Note: The numbers shown are referenced in Figure 37. DSPI modified transfer format timing — slave, CPHA = 1 PCSS PCSx Note: The numbers shown are referenced in 4 Package characteristics 4.1 Package mechanical data Freescale Semiconductor 11 5 First Data Data 9 10 First Data Data Table 39 ...

Page 122

... Package characteristics Figure 39. 144 LQFP package mechanical drawing ( 122 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

Page 123

... Figure 40. 144 LQFP package mechanical drawing ( Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Package characteristics 123 ...

Page 124

... Package characteristics Figure 41. 257 MAPBGA package mechanical drawing ( 124 MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

Page 125

... Figure 42. 257 MAPBGA package mechanical drawing ( Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 8.1 Package characteristics 125 ...

Page 126

... No FlexRay –40–125 C 120 No FlexRay –40–125 C 120 FlexRay –40–105 C 120 FlexRay –40–105 C 120 No FlexRay –40–105 C 120 No FlexRay –40–105 C 80 FlexRay –40–125 C 80 FlexRay –40–125 C Freescale Semiconductor ...

Page 127

... Updated Section 3.15, Flash memory electrical characteristics. — Updated Section 3.17.1, RESET pin characteristics. — Removed External interrupt timing (IRQ pin) timing specifications. — Updated Section 3.17.6, DSPI timing. — Updated Section 5, Ordering information. Freescale Semiconductor Flash/SRAM Package 1 MB/128 KB 144 LQFP (Pb free) 1 MB/128 KB ...

Page 128

... Added specifications for SNR, THD, SINAD, and ENOB. Revised the “Ordering information” section. 128 Table 41. Revision history (continued) Description of changes and V (was “...3.3 V”, is “...3.6 V”). DD_HV_ADR1 (was 11 mA/V, is 11.8 mA/V). mXOSCHS specification (was TBD, is minimum of 383 ns). ADC_S MPC5643L Microcontroller Data Sheet, Rev. 8.1 Freescale Semiconductor ...

Page 129

... Added the “Reset sequence” section. Revised the footnotes in the “Nexus debug port timing” table. In the “Orderable part number summary” table, added a footnote about frequency modulation to the “Speed (MHz)” column heading. Freescale Semiconductor Table 41. Revision history (continued) Description of changes . ...

Page 130

... Added the “Flash memory timing” table. Added cut2 specs for T 130 Table 41. Revision history (continued) Description of changes to T and T toT ADC_S sample ADC_C and T to the “Reset sequences” table. DRB ERLB MPC5643L Microcontroller Data Sheet, Rev. 8.1 in the “ADC conversion characteristics” conv Freescale Semiconductor ...

Page 131

... Min/Max values. Changed I In the “Supply current characteristics (cut2)” section, added a footnote that I and I characteristics” table. Freescale Semiconductor Table 41. Revision history (continued) Description of changes parameters in the “DSPI timing” table. SDC ” to “I “ ...

Page 132

... TCYC parameter description from “TCK Low to TDO Data Valid“ to “TCK Low JOV ” from the “DSPI timing” table. max MPC5643L Microcontroller Data Sheet, Rev. 8.1 Min value from V1V2 DD_LV_TYP [MHz]“ for CPU + I “. DD_LV_PLL Freescale Semiconductor ...

Page 133

... Changed C • Changed R • Removed R the sentence immediately preceding it. • Changed the C • In the “ADC conversion characteristics“ table, changed INL Min/Max values from -2/+2 to -3/+3. Freescale Semiconductor Table 41. Revision history (continued) Description of changes ” row. SS_HV_REG DD_LV_TYP ” at 150C from 80mA to 72mA. ...

Page 134

... DD_HV_FLA Table 20 (Current consumption characteristics), changed condition for SCM =25°C” J added ‘60 MHz’ to ‘conditions’ CONV specifications), changes done Table 26 (Flash memory program and ,T and added table PSRT ESRT Freescale Semiconductor ’ In ...

Page 135

... Removed Cut references from the whole document. • In from ‘1 MHz’ to ‘983.6 KHz’. 8.1 07 May 2012 • Deleted the Footer "Preliminary-Subject to Change Without Notice" label. Freescale Semiconductor Table 41. Revision history (continued) Description of changes Table 29 (MPC5643L SWG Specifications) Table 29 (MPC5643L SWG Specifications) Figure 26 in Section 3.20.4, “ ...

Page 136

... C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc ...