TRK-USB-MPC5643L Freescale Semiconductor, TRK-USB-MPC5643L Datasheet - Page 11

• Manufacturer Part Number: TRK-USB-MPC5643L
• Description: Development Boards & Kits - Other Processors StarTrakMiniUSG MPC5643L
• Manufacturer: Freescale Semiconductor

Specifications of TRK-USB-MPC5643L

• Rohs: yes
• Product: Starter Kits
• Tool Is For Evaluation Of: MPC5643L
• Core: Five Stage Pipeline
• Interface Type: LIN, DSPI
• Operating Supply Voltage: 3 V to 3.6 V
• Data Bus Width: 32 bit, 64 bit
• Description/function: Starter Kit for MPC5643L
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5643L

1.5.10
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).
It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported
to the FCCU. The following errors and indications are reported into the ECSM dedicated registers:
1.5.11
The PBRIDGE implements the following features:
1.5.12
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time
systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can
be raised temporarily so that all tasks which share the resource can not preempt each other.
The INTC provides the following features:
The INTC is replicated for each processor.
1.5.13
The following list summarizes the system clock and clock generation on this device:
Freescale Semiconductor
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ECC error status and configuration for flash memory and SRAM
ECC error reporting for flash memory
ECC error reporting for SRAM
ECC error injection for SRAM
Duplicated periphery
Master access privilege level per peripheral (per master: read access enable; write access enable)
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
Duplicated periphery
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Priority elevation for shared resource
Lock status continuously monitored by lock detect circuitry
Loss-of-clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)
Programmable output clock divider of system clock (1, 2, 4, 8)
FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock
(with max frequency 120 MHz)
On-chip crystal oscillator with automatic level control
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
Error Correction Status Module (ECSM)
Peripheral bridge (PBRIDGE)
Interrupt Controller (INTC)
System clocks and clock generation
MPC5643L Microcontroller Data Sheet, Rev. 8.1
Introduction
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