TRK-USB-MPC5643L Freescale Semiconductor, TRK-USB-MPC5643L Datasheet - Page 7

• Manufacturer Part Number: TRK-USB-MPC5643L
• Description: Development Boards & Kits - Other Processors StarTrakMiniUSG MPC5643L
• Manufacturer: Freescale Semiconductor

Specifications of TRK-USB-MPC5643L

• Rohs: yes
• Product: Starter Kits
• Tool Is For Evaluation Of: MPC5643L
• Core: Five Stage Pipeline
• Interface Type: LIN, DSPI
• Operating Supply Voltage: 3 V to 3.6 V
• Data Bus Width: 32 bit, 64 bit
• Description/function: Starter Kit for MPC5643L
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5643L

1.5.1
The e200z4d Power Architecture
1.5.2
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 independent execution units, both supporting fixed-point and floating-point operations
Dual issue 32-bit Power Architecture technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retirement
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16-bit instruction allowed
— Optimization of code size possible
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
No data cache
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
— Misaligned access support
— Single stall cycle on load to use
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)
Single precision floating-point unit
— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division
— Special square root and min/max function implemented
Signal processing support: APU-SPE 1.1
— Support for vectorized mode: as many as two floating-point instructions per clock
Vectored interrupt support
Reservation instruction to support read-modify-write constructs
Extensive system development and tracing support via Nexus debug port
High-performance e200z4d core
Crossbar switch (XBAR)
®
core provides the following features:
MPC5643L Microcontroller Data Sheet, Rev. 8.1
Introduction
7