TRK-USB-MPC5643L Freescale Semiconductor, TRK-USB-MPC5643L Datasheet - Page 103

• Manufacturer Part Number: TRK-USB-MPC5643L
• Description: Development Boards & Kits - Other Processors StarTrakMiniUSG MPC5643L
• Manufacturer: Freescale Semiconductor

Specifications of TRK-USB-MPC5643L

• Rohs: yes
• Product: Starter Kits
• Tool Is For Evaluation Of: MPC5643L
• Core: Five Stage Pipeline
• Interface Type: LIN, DSPI
• Operating Supply Voltage: 3 V to 3.6 V
• Data Bus Width: 32 bit, 64 bit
• Description/function: Starter Kit for MPC5643L
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5643L

3.19.2
The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the
figures indicate the starting point and the end point for which the duration is specified in
conditions as well as the reset trigger mapping to the different reset sequences is specified in
trigger
With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and
the internal reset sequence is finished.
The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the
signal pin RESET.
Freescale Semiconductor
1
No.
The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
1
2
3
4
5
mapping.
T
T
T
T
T
DRB
DR
ERLB
FRL
FRS
Reset Sequence Trigger
Symbol
Reset sequence description
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an
external reset generator or by the chip internal reset circuitry. A high level on this pin can
only be generated by an external pull up resistor which is strong enough to overdrive the
weak internal pull down resistor. The rising edge on RESET in the following figures
indicates the time when the device stops driving it low. The reset sequence durations given
in table
external reset generator keeping RESET asserted low beyond the last PHASE3.
Reset Sequence Start Condition
Establish IRC
and PWR
PHASE0
CC
CC
CC
CC
CC
Table 31
Destructive Reset Sequence, BIST enabled
Destructive Reset Sequence, BIST disabled
External Reset Sequence Long, BIST enabled
Functional Reset Sequence Long
Functional Reset Sequence Short
Figure 12. Destructive Reset Sequence, BIST enabled
PHASE1,2
Flash init
are applicable only if the internal reset sequence is not prolonged by an
MPC5643L Microcontroller Data Sheet, Rev. 8.1
PHASE3
Parameter
Device
Config
Table 31. RESET sequences
T
DRB, min
Self Test
RESET_B
Setup
NOTE
< T
Reset
RESET
< T
MBIST
BIST
DRB, max
LBIST
Conditions
—
—
—
PHASE1,2
Flash init
Table
Section 3.19.3, Reset sequence
Min
500
31. The start point and end point
40
41
35
1
PHASE3
Device
Config
Electrical characteristics
T
4200
Typ
150
Reset
45
47
4
Max
5000
Application
DRUN
Execution
400
51
49
10
1
Unit
ms
ms
s
s
s
103