TRK-USB-MPC5643L Freescale Semiconductor, TRK-USB-MPC5643L Datasheet - Page 10

• Manufacturer Part Number: TRK-USB-MPC5643L
• Description: Development Boards & Kits - Other Processors StarTrakMiniUSG MPC5643L
• Manufacturer: Freescale Semiconductor

Specifications of TRK-USB-MPC5643L

• Rohs: yes
• Product: Starter Kits
• Tool Is For Evaluation Of: MPC5643L
• Core: Five Stage Pipeline
• Interface Type: LIN, DSPI
• Operating Supply Voltage: 3 V to 3.6 V
• Data Bus Width: 32 bit, 64 bit
• Description/function: Starter Kit for MPC5643L
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5643L

Introduction
The platform flash controller is replicated for each processor.
1.5.8
The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
The following functions are implemented:
The platform SRAM controller is replicated for each processor.
1.5.9
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower
memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the
slave being accessed is not parked on the requesting master in the crossbar.
Table 2
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e200z4d instruction fetch
e200z4d instruction fetch
e200z4d data read
e200z4d data write
e200z4d data write
e200z4d data write
e200z4d flash memory read
e200z4d flash memory read
shows the number of additional data phase wait states required for a range of memory accesses.
Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of
platforms and frequencies.
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
Address translation from the AHB protocol on the XBAR to the SRAM array
Platform Static RAM Controller (SRAMC)
Memory subsystem access time
AHB transfer
Table 2. Platform memory access time summary
MPC5643L Microcontroller Data Sheet, Rev. 8.1
Data phase
wait states
0–1
0–2
0
3
0
0
0
3
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
of program flash memory controller arbitration)
SRAM read
SRAM 32-bit write
SRAM 64-bit write (executed as 2 x 32-bit writes)
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
Description
Freescale Semiconductor