TRK-USB-MPC5643L Freescale Semiconductor, TRK-USB-MPC5643L Datasheet - Page 21

• Manufacturer Part Number: TRK-USB-MPC5643L
• Description: Development Boards & Kits - Other Processors StarTrakMiniUSG MPC5643L
• Manufacturer: Freescale Semiconductor

Specifications of TRK-USB-MPC5643L

• Rohs: yes
• Product: Starter Kits
• Tool Is For Evaluation Of: MPC5643L
• Core: Five Stage Pipeline
• Interface Type: LIN, DSPI
• Operating Supply Voltage: 3 V to 3.6 V
• Data Bus Width: 32 bit, 64 bit
• Description/function: Starter Kit for MPC5643L
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5643L

1.5.39
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic
when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block
is compliant with the IEEE standard.
The JTAG controller provides the following features:
1.5.40
The on-chip voltage regulator module provides the following features:
Freescale Semiconductor
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— Auxiliary input port
EVTI (event in) pin
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
— Supports JTAG mode
Host processor (e200) development support features
— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool
— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
— Watchpoint messaging (WPM) via the auxiliary port
— Watchpoint trigger enable of program and/or data trace messaging
— Data tracing of instruction fetches via private opcodes
IEEE Test Access Port (TAP) interface with 5 pins:
— TDI
— TMS
— TCK
— TDO
— JCOMP
Selectable modes of operation include JTAGC/debug or normal system operation
5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS
— IDCODE
— EXTEST
— SAMPLE
— SAMPLE/PRELOAD
3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the
boundary scan register is parameterized to support a variety of boundary scan chain lengths.
TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
Single external rail required
to trace reads or writes, or both, to selected internal memory resources.
of which process ID or operating system task is activated. An ownership trace message is transmitted when a
new process/task is activated, allowing development tools to trace ownership flow.
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what
transpires between the discontinuities. Thus, static code may be traced.
IEEE 1149.1 JTAG Controller (JTAGC)
Voltage regulator / Power Management Unit (PMU)
MPC5643L Microcontroller Data Sheet, Rev. 8.1
Introduction
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