PSD835G2-90UI STMicroelectronics, PSD835G2-90UI Datasheet - Page 110

• Manufacturer Part Number: PSD835G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2016

DC and AC parameters
Table 42.
1. Any input used to select an internal PSD function.
2. WR has the same timing as E and DS signals.
3. t
4. t
5. Assuming WRITE is active before data becomes valid.
6. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
7. Assuming data is stable before active WRITE signal.
110/120
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LVLX
AVLX
LXAX
AVWL
SLWL
DVWH
WHDX
WLWH
WHAX1
WHAX2
WHPV
DVMV
AVPV
WLMV
Symbol
WHDX
WHAX2
is 6ns when writing to Output macrocell registers AB and BC.
is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
ALE or AS pulse width
Address setup time
Address hold time
Address valid to leading
edge of WR
CS valid to leading edge of WR
WR data setup time
WR data hold time
WR pulse width
Trailing edge of WR to address invalid
Trailing edge of WR to DPLD address
invalid
Trailing edge of WR to port output
valid using I/O port data register
Data valid to port output valid
using macrocell register
Preset/Clear
Address input valid to address
output delay
WR valid to port output valid using
macrocell register Preset/Clear
WRITE timing
Parameter
Conditions
(1)(2)
(2)(3)
(2)(4)
(2)(5)
(2)(7)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(6)
Min
15
12
25
28
4
7
8
4
6
0
-70
Max
27
42
20
48
Min
20
15
15
35
35
6
8
5
8
0
-90
Max
30
55
25
55
PSD835G2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns