PSD835G2-90UI STMicroelectronics, PSD835G2-90UI Datasheet - Page 41

• Manufacturer Part Number: PSD835G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2016

PSD835G2
8
8.1
Programming Flash memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. A Flash memory sector is erased to all 1s (FFh), and is
programmed by setting selected bits to '0.' Although Flash memory is erased by-sector, it is
programmed Word-by-Word.
The primary and secondary Flash memories require the MCU to send an instruction to
program a Word or to erase sectors (see
Once the MCU issues a Flash memory Program or Erase instruction, it must check the
status bits for completion. The embedded algorithms that are invoked inside the PSD
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy (PE4) output pin.
Data Polling
Polling on the Data Polling flag bit (DQ7) is a method of checking whether a Program or
Erase cycle is in progress or has completed.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the Word to be programmed in Flash memory to
check status. The Data Polling flag bit (DQ7) of this location becomes the complement of b7
of the original data byte to be programmed. The MCU continues to poll this location,
comparing the Data Polling flag bit (DQ7) and monitoring the Error flag bit (DQ5). When the
Data Polling flag bit (DQ7) matches b7 of the original data, and the Error flag bit (DQ5)
remains '0,' the embedded algorithm is complete. If the Error flag bit (DQ5) is '1,' the MCU
should test the Data Polling flag bit (DQ7) again since the Data Polling flag bit (DQ7) may
have changed simultaneously with the Error flag bit (DQ5, see
The Error flag bit (DQ5) is set if either an internal time-out occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a ’1’ to a bit
that was not erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to the Flash
memory with the byte that was intended to be written.
When using the Data Polling method after an Erase cycle,
the Data Polling flag bit (DQ7) is '0' until the Erase cycle is complete. A '1' on the Error flag
bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The
MCU can read any location within the sector being erased to get the Data Polling flag bit
(DQ7) and the Error flag bit (DQ5).
PSDsoft generates ANSI C code functions which implement these Data Polling algorithms.
Table
Figure 6
7).
shows the Data Polling algorithm.
Figure 6
Programming Flash memory
Figure
still applies. However,
6).
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