PSD835G2-90UI STMicroelectronics, PSD835G2-90UI Datasheet - Page 93

• Manufacturer Part Number: PSD835G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2016

PSD835G2
19
19.1
19.2
19.3
19.4
Figure 32. Power-Up and Warm Reset (RESET) timing
V
RESET
CC
Reset timing and device status at Reset
Power-Up Reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t
minimum) after V
clears some of the registers and sets the Flash memory into Operating mode. After the
rising edge of Reset (RESET), the PSD remains in the Reset mode for an additional period,
t
The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR, CNTL0) high, during Power-Up
Reset for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of Write Strobe (WR, CNTL0). Any Flash memory WRITE
cycle initiation is prevented automatically when V
Warm Reset
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, t
operational after warm reset.
I/O pin, register and PLD status at Reset
Table 26
and Power-down mode. PLD outputs are always valid during warm reset, and they are valid
in Power-Up Reset once the internal PSD Configuration bits are loaded. This loading of PSD
is completed typically long before V
the state of the outputs are determined by the equations specified in PSDsoft.
Reset of Flash memory erase and program cycles
A Reset (RESET) also resets the internal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash
memory to the READ mode within a period of t
OPR
(120ns maximum), before the first memory access is allowed.
Power-On Reset
shows the I/O pin, register and PLD status during Power-Up Reset, warm reset
NLNH
V
t NLNH-PO
CC
(min)
(150 ns minimum). The same t
CC
is steady. During this period, the device loads internal configurations,
Figure 32
t OPR
CC
ramps up to operating level. Once the PLD is active,
shows the timing of the Power-up and warm reset.
OPR
NLNH-A
Reset timing and device status at Reset
CC
period is needed before the device is
is below V
(25 µs minimum).
Warm Reset
t NLNH-A
t NLNH
LKO
.
NLNH-PO
t OPR
(1ms
AI02866b
93/120