PSD835G2-90UI STMicroelectronics, PSD835G2-90UI Datasheet - Page 91

• Manufacturer Part Number: PSD835G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2016

PSD835G2
18.4
18.5
PSD Chip Select Input (CSI, PD2)
PD2 of port D can be configured in PSDsoft as the PSD Chip Select Input (CSI). When low,
the signal selects and enables the internal (primary) Flash memory, secondary Flash
memory, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on
PSD Chip Select Input (CSI, PD2) disables the primary Flash memory, secondary Flash
memory, and SRAM, and reduces the PSD power consumption. However, the PLD and I/O
signals remain operational when PSD Chip Select Input (CSI, PD2) is high.
There may be a timing penalty when using PSD Chip Select Input (CSI, PD2) depending on
the speed grade of the PSD that you are using. See the timing parameter t
Input clock
The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power
consumption. CLKIN (PD1) is an input to the PLD AND Array and the output macrocells
(OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the macrocells block by setting bits 4 or 5 to a ’1’ in PMMR0.
Figure 31. Enable power-down flowchart
No
by setting PMMR0 bits 4 and 5
Disable desired inputs to PLD
Set PMMR0 Bit 1 = 1
and PMMR2 bit 0.
PSD in Power
OPTIONAL
for 15 CLKIN
Enable APD
ALE/AS idle
Down Mode
clocks?
RESET
Yes
AI02892B
Power management
SLQV
in
Table
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