PSD835G2-90UI STMicroelectronics, PSD835G2-90UI Datasheet - Page 60

• Manufacturer Part Number: PSD835G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2016

PLDs
15.5
15.6
15.7
15.8
60/120
Product term allocator
The CPLD has a product term allocator. The PSD uses the product term allocator to borrow
and place product terms from one macrocell to another. The following list summarizes how
product terms are allocated:
●
●
●
Each macrocell may only borrow product terms from certain other macrocells. Product
terms already in use by one macrocell are not available for another macrocell.
If an equation requires more product terms than are available to it, then “external” product
terms are required that consume other output macrocells (OMC). If external product terms
are used, extra delay is added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft performs this expansion as needed.
Loading and Reading the output macrocells (OMC)
The output macrocells (OMC) block occupies a memory location in the MCU address space,
as defined by the CSIOP block (see
output macrocells (OMC) can be loaded from the data bus by a MCU. Loading the output
macrocells (OMC) with data from the MCU takes priority over internal functions. As such,
the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability
to load the flip-flops and read them back is useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking protocols.
Data can be loaded to the output macrocells (OMC) on the trailing edge of the Write Strobe
(WR, CNTL0) signal.
The OMC Mask register
There is one Mask register for each of the two groups of eight output macrocells (OMC). The
Mask registers can be used to block the loading of data to individual output macrocells
(OMC). The default value for the Mask registers is 00h, which allows loading of the output
macrocells (OMC). When a given bit in a Mask register is set to a '1,' the MCU is blocked
from writing to the associated output macrocells (OMC). For example, suppose McellA0-
McellA3 are being used for a state machine. You would not want a MCU WRITE to McellA to
overwrite the state machine registers. Therefore, you would want to load the Mask register
for McellA (Mask macrocell AB) with the value 0Fh.
The Output Enable of the OMC
The output macrocells (OMC) block can be connected to an I/O port pin as a PLD output.
The output enable of each port pin driver is controlled by a single product term from the
AND Array, ORed with the Direction register output. The pin is enabled upon Power-up if no
output enable equation is defined and if the pin is declared as a PLD output in PSDsoft.
McellA0-McellA7 all have three native product terms and may borrow up to six more
McellB0-McellB3 all have four native product terms and may borrow up to five more
McellB4-McellB7 all have four native product terms and may borrow up to six more.
Section 17: I/O
ports). The flip-flops in each of the 16
PSD835G2