C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 119

• Manufacturer Part Number: C8051F060-TB
• Description: BOARD PROTOTYPING W/C8051F060
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060-TB

• Contents: Board
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F060
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Comparator interrupts can be generated on either rising-edge and falling-edge output transitions. (For
Interrupt enable and priority control, see
falling -edge interrupts are enabled using the comparator’s Rising/Falling Edge Interrupt Enable Bits (CPn-
RIE and CPnFIE) in their respective Comparator Mode Selection Register (CPTnMD), shown in
Figure 12.4. These bits allow the user to control which edge (or both) will cause a comparator interrupt.
However, the comparator interrupt must also be enabled in the Extended Interrupt Enable Register (EIE1).
The CPnFIF flag is set to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge interrupt. Once set, these bits remain set until cleared by soft-
ware. The output state of a Comparator can be obtained at any time by reading the CPnOUT bit. A Com-
parator is enabled by setting its respective CPnEN bit to logic 1, and is disabled by clearing this bit to logic
0.Upon enabling a comparator, the output of the comparator is not immediately valid. Before using a com-
parator as an interrupt or reset source, software should wait for a minimum of the specified “Power-up
time” as specified in Table 12.1, “Comparator Electrical Characteristics,” on page 122.
12.1. Comparator Inputs
The Port pins selected as comparator inputs should be configured as analog inputs in the Port 2 Input Con-
figuration Register (for details on Port configuration, see
Inputs” on page
207). The inputs for Comparator are on Port 2 as follows:
Comparator Input
CP0 +
CP1 +
CP2 +
CP0 -
CP1 -
CP2 -
Section “13.3. Interrupt Handler” on page
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Section “18.1.3. Configuring Port Pins as Digital
Port PIN
P2.6
P2.7
P2.2
P2.3
P2.4
P2.5
151). The rising and/or
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