C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 212
![BOARD PROTOTYPING W/C8051F060](/photos/28/94/289414/tqfp-100_sml.jpg)
C8051F060-TB
Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F060-TB
Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F060/1/2/3/4/5/6/7
212
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1-0:
WEAKPUD
R/W
Bit7
WEAKPUD: Weak Pull-Up Disable Bit.
0: Weak pull-ups globally enabled.
1: Weak pull-ups globally disabled.
XBARE: Crossbar Enable Bit.
0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode.
1: Crossbar enabled.
UNUSED. Read = 0, Write = don't care.
T4EXE: T4EX Input Enable Bit.
0: T4EX unavailable at Port pin.
1: T4EX routed to Port pin.
T4E: T4 Input Enable Bit.
0: T4 unavailable at Port pin.
1: T4 routed to Port pin.
UART1E: UART1 I/O Enable Bit.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX and RX routed to 2 Port pins.
Reserved
XBARE
R/W
Bit6
Figure 18.7. XBR2: Port I/O Crossbar Register 2
R/W
Bit5
-
T4EXE
R/W
Bit4
Rev. 1.2
T4E
R/W
Bit3
UART1E
R/W
Bit2
R/W
Bit1
-
SFR Address:
SFR Page:
R/W
Bit0
-
0xE3
F
Reset Value
00000000
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