C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 221
![BOARD PROTOTYPING W/C8051F060](/photos/28/94/289414/tqfp-100_sml.jpg)
C8051F060-TB
Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F060-TB
Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bits7-5:
Bits 4-0: Reserved. Write to ‘11111’.
Bits7-5:
Bits 4-0: Reserved. Write to ‘00000’.
P4.7
R/W
R/W
Bit7
Bit7
P4.[7:5]: Port4 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (open, if corresponding P4MDOUT.n bit = 0). See Figure 18.20.
Read - Returns states of I/O pins.
0: P4.n pin is logic low.
1: P4.n pin is logic high.
Note: P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory
Interface. See
page 187
P4MDOUT.[7:5]: Port4 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
P4.6
R/W
R/W
Bit6
Bit6
for more information.
Figure 18.20. P4MDOUT: Port4 Output Mode Register
Section “17. External Data Memory Interface and On-Chip XRAM” on
P4.5
R/W
R/W
Bit5
Bit5
Figure 18.19. P4: Port4 Data Register
R/W
R/W
Bit4
Bit4
-
-
Rev. 1.2
R/W
R/W
Bit3
Bit3
-
-
C8051F060/1/2/3/4/5/6/7
R/W
R/W
Bit2
Bit2
-
-
R/W
R/W
Bit1
Bit1
-
-
SFR Address:
SFR Address:
SFR Page:
SFR Page:
R/W
R/W
Bit0
Bit0
-
-
0x9C
F
0xC8
F
Addressable
Reset Value
Reset Value
00000000
11111111
Bit
221
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