C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 251

• Manufacturer Part Number: C8051F060-TB
• Description: BOARD PROTOTYPING W/C8051F060
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060-TB

• Contents: Board
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F060
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
Enhanced Serial Peripheral Interface (SPI0)
SYSCLK
Clock Divide
SPI0CKR
SFR Bus
SPI0DAT
Logic
Write
Transmit Data Buffer
Receive Data Buffer
7
6
Figure 21.1. SPI Block Diagram
Shift Register
5
SPI CONTROL LOGIC
4
3
Data Path
2
SFR Bus
Control
SPI0CFG
SPI0DAT
1
SPI0DAT
Read
0
Rev. 1.2
Tx Data
Rx Data
C8051F060/1/2/3/4/5/6/7
Pin Interface
Control
Control
Logic
Pin
SPI0CN
MOSI
MISO
SCK
NSS
O
C
R
S
S
B
A
R
SPI IRQ
Port I/O
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