C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 293
![BOARD PROTOTYPING W/C8051F060](/photos/28/94/289414/tqfp-100_sml.jpg)
C8051F060-TB
Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F060-TB
Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 293 of 328
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Bits7-5:
Bit4:
Bit3:
Bit2:
Bits1-0:
†Note:
R/W
Bit7
-
UNUSED. Read = 000b, Write = don’t care.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
UNUSED. Read = 0b, Write = don’t care.
SCA1-SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
External clock divided by 8 is synchronized with the system clock, and external clock must
be less than or equal to the system clock frequency to operate the timer in this mode.
SCA1
0
0
1
1
R/W
Bit6
-
SCA0
0
1
0
1
R/W
Bit5
Figure 24.6. CKCON: Clock Control Register
-
External clock divided by 8†
System clock divided by 12
System clock divided by 48
System clock divided by 4
T1M
R/W
Bit4
Prescaled Clock
Rev. 1.2
T0M
R/W
Bit3
C8051F060/1/2/3/4/5/6/7
R/W
Bit2
-
SCA1
R/W
Bit1
SFR Address:
SFR Page:
SCA0
R/W
Bit0
0x8E
0
Reset Value
00000000
293
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