C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 272

• Manufacturer Part Number: C8051F060-TB
• Description: BOARD PROTOTYPING W/C8051F060
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060-TB

• Contents: Board
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F060
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F060/1/2/3/4/5/6/7
address as valid. If a master were to then send an address of “11111111”, all three slave devices would rec-
ognize the address as a valid broadcast address.
22.3. Frame and Transmission Error Detection
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SCON0) reads ‘1’ if user software writes data to the
SBUF0 register while a transmit is in progress. Note that the TXCOL0 bit is also used as the SM20 bit
when written by user software. This bit does not generate an interrupt.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SCON0) reads ‘1’ if a new data byte is latched into the receive
buffer before software has read the previous byte. Note that the RXOV0 bit is also used as the SM10 bit
when written by user software. The Frame Error bit (FE0 in register SSTA0) reads ‘1’ if an invalid (low)
STOP bit is detected. Note that the FE0 bit is also used as the SM00 bit when written by user software.
The RXOV0 and FE0 bits do not generate interrupts.
272
RX
Master
Device
Figure 22.7. UART Multi-Processor Mode Interconnect Diagram
TX
RX
Device
Slave
TX
Rev. 1.2
RX
Device
Slave
TX
RX
Device
Slave
TX
+5V