MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 17
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.3
14.3.1.4
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.3.9
14.3.10
14.3.10.1
14.3.11
14.3.11.1
14.3.12
14.3.13
14.3.14
14.3.15
14.3.16
14.3.17
14.3.18
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.4.1
Freescale Semiconductor
Paragraph
Number
QADC64E Block Diagram ........................................................................................... 14-1
Key Features and Quick Reference Diagrams .............................................................. 14-2
Programming the QADC64E Registers ........................................................................ 14-7
Digital Subsystem ....................................................................................................... 14-38
Features of the QADC64E Enhanced Mode Operation ............................................ 14-2
Memory Map ............................................................................................................ 14-3
Legacy and Enhanced Modes of Operation .............................................................. 14-4
Using the Queue and Result Word Table ................................................................. 14-5
External Multiplexing ............................................................................................... 14-5
QADC64E Interrupt Register ................................................................................. 14-11
Port Data Register ................................................................................................... 14-12
Port Data Direction Register ................................................................................... 14-13
Control Register 0 ................................................................................................... 14-14
Control Register 1 ................................................................................................... 14-16
Control Register 2 ................................................................................................... 14-18
Status Registers (QASR0 and QASR1) .................................................................. 14-22
Conversion Command Word Table ........................................................................ 14-28
Result Word Table .................................................................................................. 14-34
Analog-to-Digital Converter Operation .................................................................. 14-36
Channel Decode and Multiplexer ........................................................................... 14-37
Sample Buffer Amplifier ........................................................................................ 14-37
Digital to Analog Converter (DAC) Array ............................................................. 14-37
Comparator ............................................................................................................. 14-38
Bias ......................................................................................................................... 14-38
Successive Approximation Register ...................................................................... 14-38
State Machine ......................................................................................................... 14-38
Queue Priority ......................................................................................................... 14-39
Sub-Queues That are Paused .................................................................................. 14-39
Boundary Conditions .............................................................................................. 14-41
Scan Modes ............................................................................................................. 14-42
QADC64E Module Configuration Register ........................................................... 14-8
Low Power Stop Mode ......................................................................................... 14-8
Freeze Mode ......................................................................................................... 14-9
Switching Between Legacy and Enhanced Modes of Operation .......................... 14-9
Supervisor/Unrestricted Address Space ............................................................. 14-10
Analog Subsystem .............................................................................................. 14-36
Conversion Cycle Times ..................................................................................... 14-36
Disabled Mode .................................................................................................... 14-42
QADC64E Enhanced Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 14
Title
Number
Page
xvii
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