MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 19
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.5
15.5.1
15.5.2
15.5.3
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.1.5
15.6.2
15.6.2.1
15.6.2.2
15.6.2.3
15.6.3
15.6.4
15.6.4.1
15.6.4.2
15.6.4.3
15.6.5
15.6.5.1
15.6.5.2
15.6.5.3
15.6.5.4
15.6.5.5
15.6.5.6
15.6.5.7
15.6.5.8
15.6.6
15.6.6.1
15.6.7
15.6.8
15.7
15.7.1
Freescale Semiconductor
Paragraph
Number
QSMCM Pin Control Registers .................................................................................. 15-10
Queued Serial Peripheral Interface ............................................................................. 15-14
Serial Communication Interface ................................................................................. 15-42
Access Protection ...................................................................................................... 15-6
QSMCM Interrupts ................................................................................................... 15-7
QSPI Interrupt Generation ........................................................................................ 15-8
QSMCM Configuration Register (QSMCMMCR) .................................................. 15-8
QSMCM Test Register (QTEST) ............................................................................. 15-9
QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL) ..................................... 15-9
Port QS Data Register (PORTQS) .......................................................................... 15-11
PORTQS Pin Assignment Register (PQSPAR) ..................................................... 15-12
PORTQS Data Direction Register (DDRQS) ......................................................... 15-13
QSPI Registers ....................................................................................................... 15-16
QSPI RAM .............................................................................................................. 15-22
QSPI Pins ................................................................................................................ 15-24
QSPI Operation ....................................................................................................... 15-25
Master Mode Operation .......................................................................................... 15-34
Slave Mode ............................................................................................................. 15-39
Slave Wraparound Mode ........................................................................................ 15-41
Mode Fault .............................................................................................................. 15-42
SCI Registers .......................................................................................................... 15-45
QSPI Control Register 0 (SPCR0) ...................................................................... 15-17
QSPI Control Register 1 (SPCR1) ...................................................................... 15-19
QSPI Control Register 2 (SPCR2) ...................................................................... 15-20
QSPI Control Register 3 (SPCR3) ...................................................................... 15-20
QSPI Status Register (SPSR) .............................................................................. 15-21
Receive RAM ..................................................................................................... 15-23
Transmit RAM .................................................................................................... 15-23
Command RAM .................................................................................................. 15-23
Enabling, Disabling, and Halting the SPI ........................................................... 15-26
QSPI Interrupts ................................................................................................... 15-26
QSPI Flow .......................................................................................................... 15-27
Clock Phase and Polarity .................................................................................... 15-35
Baud Rate Selection ............................................................................................ 15-35
Delay Before Transfer ........................................................................................ 15-36
Delay After Transfer ........................................................................................... 15-36
Transfer Length .................................................................................................. 15-37
Peripheral Chip Selects ....................................................................................... 15-37
Optional Enhanced Peripheral Chip Selects ....................................................... 15-37
Master Wraparound Mode .................................................................................. 15-38
Description of Slave Operation .......................................................................... 15-40
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Title
Number
Page
xix
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