MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 44
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Figure
Number
Single Beat Basic Write Cycle Timing – One Wait State ...................................................... 9-14
Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size ......................................... 9-15
Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set .............. 9-17
Basic Flow Diagram Of A Burst-Read Cycle......................................................................... 9-21
Burst-Read Cycle – 32-Bit Port Size – Zero Wait State......................................................... 9-21
Burst-Read Cycle – 32-Bit Port Size – One Wait State.......................................................... 9-22
Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats ....................................... 9-23
Burst-Read Cycle – 16-Bit Port Size ...................................................................................... 9-24
Basic Flow Diagram of a Burst-Write Cycle.......................................................................... 9-26
Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
(Only for External Master Memory Controller Service Support)........................................... 9-26
Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst)................................................ 9-27
Non-Wrap Burst with Three Beats ......................................................................................... 9-28
Non-Wrap Burst with One Data Beat ..................................................................................... 9-29
Internal Operand Representation ............................................................................................ 9-30
Interface To Different Port Size Devices................................................................................ 9-31
Bus Arbitration Flowchart ...................................................................................................... 9-33
Master Signals Basic Connection ........................................................................................... 9-34
Bus Arbitration Timing Diagram............................................................................................ 9-35
Internal Bus Arbitration State Machine .................................................................................. 9-36
Termination Signals Protocol Basic Connection .................................................................... 9-41
Termination Signals Protocol Timing Diagram...................................................................... 9-41
Reservation on Local Bus ....................................................................................................... 9-43
Reservation on Multi-level Bus Hierarchy ............................................................................. 9-44
Retry Transfer Timing – Internal Arbiter ............................................................................... 9-46
Retry Transfer Timing – External Arbiter .............................................................................. 9-47
Retry on Burst Cycle............................................................................................................... 9-48
Basic Flow of an External Master Read Access ..................................................................... 9-50
Basic Flow of an External Master Write Access .................................................................... 9-51
Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States) ......... 9-52
Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)............ 9-53
Flow of Retry of External Master Read Access ..................................................................... 9-54
Retry of External Master Access (Internal Arbiter)................................................................ 9-55
Instruction Show Cycle Transaction....................................................................................... 9-57
Data Show Cycle Transaction................................................................................................. 9-58
Memory Controller Function within the USIU....................................................................... 10-1
Memory Controller Block Diagram........................................................................................ 10-2
MPC561/MPC563 Simple System Configuration .................................................................. 10-3
Bank Base Address and Match Structure ............................................................................... 10-4
A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts) ............................................. 10-9
MPC561/MPC563 Reference Manual, Rev. 1.2
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