MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 583

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Trigger events which occur during the execution of a sub-queue are ignored, except that the trigger overrun
flag is set. When a continuous-scan mode is selected, a trigger event occurring after the completion of the
last sub-queue (after the queue completion flag is set), causes the execution to continue with the first
sub-queue, starting with the first CCW in the queue.
When the QADC64E encounters a CCW with the pause bit set, the queue enters the paused state after
completing the conversion specified in the CCW with the pause bit. The pause flag is set and a pause
software interrupt may optionally be issued. The status of the queue is shown to be paused, indicating
completion of a sub-queue. The QADC64E then waits for another trigger event to again begin execution
of the next sub-queue.
14.4.3
The following are queue operation boundary conditions:
Boundary conditions also exist for combinations of pause and end-of-queue. One case is when a pause bit
is in one CCW and an end-of-queue condition is in the next CCW. The conversion specified by the CCW
with the pause bit set completes normally. The pause flag is set. However, since the end-of-queue condition
is recognized, the completion flag is also set and the queue status becomes idle, not paused. Examples of
this situation include:
Freescale Semiconductor
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The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code. The queue becomes
active and the first CCW is read. The end-of-queue is recognized, the completion flag is set, and
the queue becomes idle. A conversion is not performed.
BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger event occurs on
queue 2. Refer to
end-of-queue condition is recognized, a conversion is performed, the completion flag is set, and
the queue becomes idle.
BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0, the end-of-queue
condition is recognized, the completion flag is set, and the queue becomes idle. A conversion is not
performed.
BQ2 is set beyond the end of the CCW table (64 – 127) and a trigger event occurs on queue 2. The
end-of-queue condition is recognized immediately, the completion flag is set, and the queue
becomes idle. A conversion is not performed.
The pause bit is set in CCW5 and the EOQ code is in CCW6
The pause is set in CCW63
During queue 1 operation, the pause bit is set in CCW20 and BQ2 points to CCW21
Boundary Conditions
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC64E behavior. For example, if BQ2
is set to CCW0, CCW0 contains the EOQ code, and a trigger event occurs
on queue 1, the QADC64E reads CCW0 and detects both end-of-queue
conditions. The completion flag is set and queue 1 becomes idle.
Section 14.3.7, “Control Register
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
2” for more information on BQ2. The
QADC64E Enhanced Mode Operation
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