DP83865-EB National Semiconductor, DP83865-EB Datasheet
DP83865-EB
Specifications of DP83865-EB
Related parts for DP83865-EB
DP83865-EB Summary of contents
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... The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductor’s South Portland, Maine facility ...
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Block Diagram MGMT INTERFACE C MGMT & PHY CNTRL 100BASE-TX 10BASE-T Block MII 100BASE-TX PCS 100BASE-TX PMA 100BASE-TX PMD MLT-3 100 Mb/s www.national.com COMBINED MII / GMII / RGMII INTERFACE MII 1000BASE-T Block Block MII 1000BASE-T 10BASE-T PLS 1000BASE-T 10BASE-T ...
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... DP83865’s Link LED will blink on and off 7.16 How do I quickly determine the quality of the link over the cable ? . . . . . . . . . . . . . . . . . . . . . . 83 7.17 What is the power up sequence for DP83865 7.18 What are some other applicable documents 8.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 86 3 www.national.com ...
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... TMS 27 TDO 28 IO_VDD 29 VSS 30 TDI 31 TRST 32 RESET 33 VDD_SEL_STRAP 34 CORE_VDD 35 VSS 36 IO_VDD 37 VSS 38 www.national.com DP83865DVH Gig PHYTER V Figure 1. DP83865 Pinout Order Part Number: DP83865DVH 4 102 BG_REF 101 2V5_AVDD1 100 1V8_AVDD3 99 VSS 98 1V8_AVDD2 97 VSS 96 2V5_AVDD2 95 PHYADDR4_STRAP 94 MULTI_EN_STRAP / TX_TRIGGER 93 VSS 92 CORE_VDD 91 VSS 90 IO_VDD 89 MDIX_EN_STRAP ...
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... Pin Description The DP83865 pins are classified into the following interface categories (each is described in the sections that follow): — MAC Interfaces — Management Interface — Media Dependent Interface — JTAG Interface — Clock Interface — Device Configuration and LED Interface — ...
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Pin Description (Continued) PQFP Signal Name Type Pin # TXD0/TX0 I TXD1/TX1 TXD2/TX2 TXD3/TX3 TXD4 TXD5 TXD6 TXD7 TX_EN/TXEN_ER I GTX_CLK/TCK I TX_ER I RX_CLK O_Z RXD0/RX0 O_Z RXD1/RX1 RXD2/RX2 RXD3/RX3 RXD4 RXD5 RXD6 RXD7 RX_ER/RXDV_ER O_Z RX_DV/RCK O_Z ...
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... Description Media Dependent Interface: Differential receive and transmit signals. The TP Interface connects the DP83865 to the CAT-5 cable through a single common magnetics transformer. These differential inputs and outputs are con- figurable to 10BASE-T, 100BASE-TX or 1000BASE-T signalling: The DP83865 will automatically configure the driver outputs for the proper sig- nal type as a result of either forced configuration or Auto-Negotiation ...
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Pin Description (Continued) PQFP Signal Name Type PIn # TCK I 1.5 Clock Interface PQFP Signal Name Type Pin # CLK_IN I CLK_OUT O CLK_TO_MAC O 1.6 Device Configuration and LED Interface (See section “3.7 PHY Address, Strapping Options ...
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Pin Description (Continued) PQFP Signal Name Type Pin # ACTIVITY_LED / I/O, 7 SPEED0_STRAP S, PD LINK10_LED /RLED/ I/O, 8 SPEED1_STRAP S, PD LINK100_LED / I/O, 9 DUPLEX_STRAP S, PU LINK1000_LED / I/O, 10 AN_EN_STRAP S, PU Description SPEED ...
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... Type Pin # RESET I www.national.com 13 PHY ADDRESS [4:0]: The DP83865 provides five PHY address-sensing pins for multiple PHY applications. The setting on these five pins provides the base address of the PHY. 14 The five PHYAD[4:0] bits are registered as inputs at reset with PHYADDR4 be- 17 ing the MSB of the 5-bit PHY address. ...
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Pin Description (Continued) 1.8 Power and Ground Pins (See section “5.3 Power Supply Decoupling” on page 64.) Signal Name PQFP Pin # IO_VDD 4, 15, 21, 29, 37, 42, 53, 58, 69, 77, 83, 90 CORE_VDD 11, 19, 25, ...
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Pin Description (Continued) 1.10 Pin Assignments in the Pin Number Order Pin # Data Sheet Pin Name 1 NON_IEEE_STRAP 2 RESERVED 3 INTERRUPT 4 IO_VDD 5 VSS 6 TX_TCLK 7 ACTIVITY_LED / SPEED0_STRAP 8 LINK10_LED / RLED/SPEED1_STRAP 9 LINK100_LED ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 23 RESERVED 24 TCK 25 CORE_VDD 26 VSS 27 TMS 28 TDO 29 IO_VDD 30 VSS 31 TDI 32 TRST 33 RESET 34 VDD_SEL_STRAP 35 CORE_VDD 36 VSS 37 IO_VDD ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 45 RXD7 46 RXD6 47 RXD5 48 CORE_VDD 49 VSS 50 RXD4 51 RXD3/RX3 52 RXD2/RX2 53 IO_VDD 54 VSS 55 RXD1/RX1 56 RXD0/RX0 www.national.com Table 1. Type Connection / ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 57 RX_CLK 58 IO_VDD 59 VSS 60 TX_CLK/RGMII_SEL1 61 TX_ER 62 TX_EN/TXEN_ER 63 CORE_VDD 64 VSS 65 TXD7 66 TXD6 67 TXD5 68 TXD4 69 IO_VDD 70 VSS 71 TXD3/TX3 ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 79 GTX_CLK/TCK 80 MDIO 81 MDC 82 VSS 83 IO_VDD 84 RESERVED 85 CLK_TO_MAC 86 CLK_IN 87 CLK_OUT 88 MAC_CLK_EN_STRAP 89 MDIX_EN_STRAP 90 IO_VDD 91 VSS 92 CORE_VDD 93 VSS ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 107 VSS 108 MDIA_P 109 MDIA_N 110 VSS 111 RX_VDD 112 VSS 113 VSS 114 MDIB_P 115 MDIB_N 116 VSS 117 RX_VDD 118 VSS 119 VSS 120 MDIC_P 121 MDIC_N ...
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... Register Block 2.1 Register Definitions Register maps and address definitions are given in the following table: Table 2. Register Block - DP83865 Register Map Offset Access Hex Decimal 0x00 0 RW 0x01 1 RO 0x02 2 RO 0x03 3 RO 0x04 4 RW 0x05 5 RW 0x06 6 RW 0x07 ...
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Register Block (Continued) 19 www.national.com ...
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Register Block (Continued) www.national.com 20 ...
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Register Block (Continued) 2.3 Register Description In the register description under the ‘Default’ heading, the following definitions hold true: — Read Write access — Read Only access — Latched High until read, based ...
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... IF Auto-Negotiation is disabled Reserved by IEEE: Write ignored, read 100BASE-T4 Capable Device not able to perform 100BASE-T4 mode. DP83865 does not support 100BASE-T4 mode and bit should al- ways be read back as “0” 100BASE-X Full Duplex Capable Device able to perform 100BASE-X in Full Duplex mode 100BASE-X Half Duplex Capable Device able to perform 100BASE-X in Half Duplex mode ...
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... DP83865 does not support 100BASE-T2 mode and bit should al- ways be read back as “0” 100BASE-T2 Half Duplex Capable Device unable to perform 100BASE-T2 Half Duplex mode. DP83865 does not support 100BASE-T2 mode and bit should al- ways be read back as “0” 1000BASE-T Extended Status Register Device supports Extended Status Register 0x0F. ...
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... OUI[3:18] The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83865. The Identifier consists of a con- catenation of the Organizationally Unique Identifier (OUI), the vendor’s model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to sup- port network management. National’ ...
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Register Block (Continued) Table 7. Auto-Negotiation Advertisement Register (ANAR) address 0x04 Bit Bit Name 8 100BASE-TX Full Duplex 7 100BASE-TX (Half Duplex) 6 10BASE-T Full Duplex 5 10BASE-T (Half Duplex) 4:0 PSB[4:0] This register contains the advertised abilities of ...
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Register Block (Continued) Table 8. Auto-Negotiation Link Partner Ability Register (ANLPAR) address 0x05 Bit Bit Name ACK Reserved 11 ASY_PAUSE 10 PAUSE 9 100BASE-T4 8 100BASE-TX Full Duplex 7 100BASE-TX (Half Duplex) 6 ...
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Register Block (Continued) Table 9. Auto-Negotiate Expansion Register (ANER) address 0x06 Bit Bit Name 15:5 Reserved 4 PDF 3 LP_NP Able 2 NP Able 1 PAGE_RX 0 LP_AN Able This register contains additional Local Device and Link Partner status ...
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Register Block (Continued) Table 10. Auto-Negotiation Next Page Transmit Register (ANNPTR) address 0x07 Bit Bit Name 11 TOG_TX 10:0 CODE[10:0] This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 11. ...
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Register Block (Continued) Table 11. Auto-Negotiation Next Page Receive Register (ANNPRR) address 0x08 Bit Bit Name 11 TOG_RX 10:0 CODE[10:0] This register contains the next page information sent by its Link Partner during Auto-Negotiation. Table 12. 1000BASE-T Control Register ...
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Register Block (Continued) Table 12. 1000BASE-T Control Register (1KTCR) address 0x09 Bit Bit Name 9 1000BASE-T Full Duplex 8 1000BASE-T Half Duplex 7:0 Reserved Table 13. 1000BASE-T Status Register (1KSTSR) address 0x0A (10’d) Bit Bit Name 15 Master / ...
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... P 1000BASE-X Half Duplex Support 1000BASE-X is supported by the local device. 0 =1000BASE-X is not supported. DP83865 does not support 1000BASE-X and bit should always be read back as “0” 1000BASE-T Full Duplex Support 1000BASE-T is supported by the local device. 0 =1000BASE-T is not supported. ...
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Register Block (Continued) Table 16. Link and Auto-Negotiation Status Register (LINK_AN) address 0x11 (17’d) Bit Bit Name 15:12 TP Polarity[3:0] 11 Reserved (Power Down Status) 10 MDIX Status 9 FIFO Error 8 Reserved 7 Shallow Loopback Status 6 Deep ...
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Register Block (Continued) Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d) Bit Bit Name 15 Auto-MDIX Enable 14 Manual MDIX Value 13:12 RGMII_EN[1:0] 11:10 Reserved 9 Non-Compliant Mode STRAP[0], RW Non-Compliant Mode Enable: This bit enables the PHY ...
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Register Block (Continued) Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d) Bit Bit Name 5 Shallow Deep Loop- back Enable 4 X_Mac 3:1 Reserved 0 Jabber Disable Table 18. LED Control Register (LED_CTRL) address 0x13 (19’d) Bit Bit ...
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Register Block (Continued) Table 18. LED Control Register (LED_CTRL) address 0x13 (19’d) Bit Bit Name 5 reduced LED enable 4 led_on_crc 3 led_on_ie 2 an_fallback_an 1 an_fallback_crc 0 an_fallback_ie Table 19. Interrupt Status Register (INT_STATUS) address 0x14 (20’d) Bit ...
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Register Block (Continued) Table 20. Interrupt Mask Register (INT_MASK) address 0x15 (21’d) Bit Bit Name 15 spd_cng_int_msk 14 lnk_cng_int_msk 13 dplx_cng_int_msk 12 mdix_cng_int_msk 11 pol_cng_int_msk 10 prl_det_flt_int_msk 9 mas_sla_err_int_msk 8 no_hcd_int_msk 7 no_lnk_int_msk 6 jabber_cng_int_msk 5 nxt_pg_rcvd_int_msk 4 an_cmpl_int_msk ...
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Register Block (Continued) Table 22. Interrupt Clear Register (INT_CLEAR) address 0x17 (23’d) Bit Bit Name 15 spd_cng_int_clr 14 lnk_cng_int_clr 13 dplx_cng_int_clr 12 mdix_cng_int_clr 11 pol_cng_int_clr 10 prl_det_flt_int_clr 9 mas_sla_err_int_clr 8 no_hcd_int_clr 7 no_lnk_int_clr 6 jabber_cng_int_clr 5 nxt_pg_rcvd_int_clr 4 an_cmpl_int_clr ...
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Register Block (Continued) Table 24. BIST Configuration Register 1 (BIST_CFG1) address 0x19 (25’d) Bit Bit Name 10 tx_bist_pak_type 9:8 Reserved 7:0 tx_bist_pak Table 25. BIST Configuration Register 2 (BIST_CFG2) address 0x1A (26’d) Bit Bit Name 15 rx_bist_en 14 bist_cnt_sel ...
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Register Block (Continued) Table 28. PHY Support Register #2 (PHY_SUP) address 0x1F (31’d) Bit Bit Name 15:5 Reserved 4:0 PHY Address Default 0, RO Write as 0, ignore on read. STRAP[0_0001], PHY Address: Defines the port on which the ...
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... The following is an example of step-by-step precedure enabling the Speed Fallback mode: — 1) Power down the DP83865 by setting register 0x00. This is to ensure that the memory access does not interfere with the normal operation. — 2) Write to register 0x16 the value 0x0000. This allows access to expanded memory for 8-bit read/write. — ...
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... For further details regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3u specification. The DP83865 supports six different Ethernet protocols: 10BASE-T Full Duplex, 10BASE-T Half Duplex, 100BASE-TX Full Duplex, 100BASE-TX Half Duplex, 1000BASE-T Full Duplex, and 1000BASE-T Half Duplex ...
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Configuration (Continued) Table 33. Speed/Duplex Selection, AN_EN = 1 DUP Speed[1] Speed[ 1000/100/10 HDX 1000/100 HDX 1000 HDX 1000/10 HDX 1000/100/10 FDX + HDX ...
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... Negotiation is completed, it may be restarted at any time by writing ‘1’ to bit 9 of the BMCR 0x00. A restart Auto-Negotiation request from any entity, such as a management agent, will cause DP83865 to halt data transmission or link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail mode and the resume Auto-Negotiation ...
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... A Parallel Detect Fault has occurred (bit 4, ANER 0x06). 1000BASE-T FD — The Link Partner supports the Next Page function (bit 3, ANER 0x06). — The DP83865 supports the Next Page function (bit 2, 10BASE-T FD ANER 0x06). — The current page being exchanged by Auto-Negotiation has been received (bit1, ANER 0x06). — ...
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... The PHY address of DP83865 port can be configured to any of the 31 possible PHY addresses (except 00h which puts the PHY in isolation mode at power-up). However, if more than one DP83865 is used on a board and if MDIO is bused in a system, each of the DP83865’s address must be different. ...
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... RGMII interface disables GMII and MII inter- faces. 3.11 Clock to MAC Enable The DP83865 has a clock output (pin 85) that can be used as a reference clock for other devices such as MAC or switch silicon. The Clock to MAC output can be enabled through strapping pins. ...
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... Low Power Mode / WOL The GigPHYTER V supports the Wake on LAN (WOL) fea- ture of a higher layer device. In order to achive the least possible power consumption the DP83865 must be put in 10BASE-T mode (Half or Full Duplex). In this mode the device uses a maximum of 146mW of power. ...
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... JTAG interface, clock interface, device configuration and reset pins. 3.22 Non-compliant inter-operability mode In this mode the DP83865 allows with other vendor’s first generation 1000 Mbps PHYs. National’s DP83865 is com- pliant to IEEE 802.3ab and optionally inter-operable with non-compliant PHYs. ...
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... Functional Description The DP83865 is a full featured 10/100/1000 Ethernet Phys- ical layer (PHY) chip. It consists of a digital 10/100/1000 Mb/s core with a common TP interface. It also has a com- bined versitle MAC interface that is capable of interfacing with MII and GMII controller interfaces. In this section, the following topics are covered: — ...
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Functional Description Data Scrambler and Symbol LSFR Scr [32:0] n Sign Scrambler Word Generator g( ...
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Functional Description PARTIAL RESPONSE PULSE SHAPE CODING 5-LEVEL PAM-5 TO 17-LEVEL PAM SIGN PAM-5 SCRAMBLER 3-bits/sample 0.75 0.75 X(k) + 0.25 X(k-1) PMA Transmitter Block PAM-5 w ith PR (.7 5+.2 5T) 1.200 1.000 0.800 0.600 0.400 0.200 0.000 ...
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... PAM-5 coded data stream. Each DAC is clocked with the internal 125 MHz clock in the MASTER mode, and the recovered receive clock in the SLAVE mode operation. The DP83865 incorporates a sophisticated Clock Genera- tion Module (CGM) which supports 10/100/1000 modes of operation with an external 25 MHz clock reference (±50 ppm) ...
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... Mbps Mode Timing At the time of the publication of RGMII standard version 1.3, there are two different implmentations of RGMII, HP and 3COM. The difference is in setup and hold timing. The DP83865 implemented the HP timing. The following is an explanation of the RGMII interface of the DP83865. 53 TD0 GPHY TD1 ...
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... The pulse is used to check the integrity of the connection to the remote MAU. 4.7.3 Transmit Driver The 10 Mb/s transmit driver in the DP83865 shares the 100/1000 Mb/s common driver. 4.7.4 Jabber Detect The Jabber Detect function disables the transmitter if it attempts to transmit a much longer than legal sized packet ...
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Functional Description TX_CLK DIVIDER FROM PGM 100BASE-X LOOPBACK Figure 6. 10BASE-T/100BASE-TX Transmit Block Diagram 4.7.5 100BASE-T Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This ...
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... Functional Description dB. The DP83865 uses the PHYADDR[4:0] value to set a unique seed value for the scramblers. The resulting energy generated by each channel is out of phase with respect to each channel, thus reducing the overall electro-magnetic radiation. 4.7.8 NRZ to NRZI Encoder After the transmit data stream has been serialized and ...
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... TX_ER Assertion of the TX_ER input while the TX_EN is also asserted will cause the DP83865 to substitute HALT code- groups for the 5B data present at TXD[3:0]. However, the Start-of-Stream Delimiter (SSD) /J/K/ and End-of-Stream Delimiter (ESD) /T/R/ will not be substituted with HALT code-groups ...
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... BASE-TX ADC Block The DP83865 requires no external attenuation circuitry at its receive inputs, MDI+/-. It accepts TP-PMD compliant waveforms directly from a 1:1 transformer. The analog MLT-3 signal (with noise and system impairments) is received and converted to the digital domain via an Analog www ...
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... Signal Detect In 100BASE-TX mode, the link is established by detecting the scrambled idles from the link partner. In 100BASE-T mode, the signal detect function of the DP83865 meets the specifications mandated by the ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 (Continued) Figure 9. 100BASE-TX BLW Event ...
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... The CRM is implemented using an advanced digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuitry. Using digital PLL circuitry allows the DP83865 to be manufactured and specified to tighter toler- ances. 4.8.9 MLT-3 to NRZ Decoder The DP83865 decodes the MLT-3 information from the DSP block to binary NRZI form and finally to NRZ data ...
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... MDIO interface, the station manage- ment entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83865 with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecu- tive MDC clock cycles simply allowing the MDIO pull- up resistor to pull the MDIO pin high during which time 32 MDC clock cycles are provided ...
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... Opcode PHY Address Idle Start (Write) (PHYAD = 0Ch) 4.9.4 PHY Address Sensing The DP83865 provides five PHY address pins to set the PHY address. The information is latched into the STRAP_REG 0x10.4:0 at device power-up or reset. The DP83865 supports PHY Address 1(<00001>) through 31(<11111>). Note that PHY address 0 by default is the broadcast write address and should not be used as the PHY address ...
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... RESET pin. 5.2 Clocks The CLOCK_IN pin is the 25 MHz clock input to the DP83865 used by the internal PLL. This input should come from a 25 MHz clock oscillator or a crystal. (Check Section 5.13.1 for component requirements.) When using a crystal, CLOCK_OUT must be connected to the second terminal of the crystal ...
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... The decision is left to the board designer based on the evaluation of a specific case. 5.5 PCB Layer Stacking Via to plane To route traces for the DP83865 PQFP package, a mini- mum of four PCB layers is necessary. To meet perfor- mance requirements, a six layer board design is recommended. The following is the layer stacking recom- mendations for four and six-layer boards ...
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... F 0.01 F GND 1V8_AVDD1 IO_VDD 0.1 F 0.01 F GND 2V5_AVDD2 2V5_AVDD1 9.76 k 0.01 F BG_REF 1% GND 1V8_AVDD3 22 F GND Figure 15. Power Supply Filtering DP83865 and GMAC PCI NIC Card PHY MAC 2 0.1 F 0.01 F GND 0.01 F GND 0.01 F GND www.national.com ...
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... Each MDI pair should be placed as close as possible in parallel to minimmize EMI and crosstalk. Each member of a pair should be matched in length to prevent mis- match in delay that would cause common mode noise. — Ideally there should be no crossover or via on the signal paths. 66 DP83865 MDI_A+ MDI_A- = 2.5 V 49.9 49.9 0.01 uF ...
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Design Guide (Continued) 5.8 RJ-45 Connections The magnetics isolates local circuitry from other equipment that Ethernet connects to. The IEEE isolation test places stress on the isolated side to test the dielectic strength of the isolation. The center tap ...
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... The number of unused pins and which pins become unused pins highly depend on the individual application the DP83865 is used in. Refer to Section 1.0 for each individ- ual pin that is not used. Reserved pins must be left floating. ...
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Design Guide (Continued) Table 56. Recommended Crystal Oscillators Manufacturer Vite Technology 25 MHz 7 Oscillator www.viteonline.com Raltron 25 MHz 7 Oscillator www.raltron.com Pericom www.saronix.com Abracon www.abracon.com Pletronics www.pletronics.com Note: Contact Oscillator manufactures for ...
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Design Guide (Continued) 5.13.2 Magnetics It is important to select the compoment that meets the requirements. Per IEEE 802.3ab Clause 40.8, the compo- nent requirements are listed in Table 57. transformer winding should have the configuration shown in Figure ...
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Electrical Specifications Absolute Maximum Ratings Supply Voltage IO_VDD Supply Voltage CORE_VDD, 1V8_AVDD1, 1V8_AVDD2 Supply Voltage 2V5_AVDD1, 2V5_AVDD2 Input Voltage (DC ) -0.5V to IO_VDD + 0.5V IN Output Voltage (DC ) -0.5V to IO_VDD + 0.5V OUT Storage Temperature ...
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Electrical Specifications Symbol Pin Types Parameter V I Input Low IL I/O Voltage non-R/GMII I/O_Z V O, Output High OH I/O Voltage non-R/GMII I/O_Z V O, Output Low OL I/O Voltage non-R/GMII I/O_Z R strap Strap PU/PD internal resistor ...
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Electrical Specifications 6.2 Reset Timing V 1.8V (core, analog), DD 2.5V (I/O, analog), 3.3V (I/O if applicable) CLK_IN RESET MDC Latch-In of Hardware Configuration Pins CLK_TO_MAC Parameter Description T1 Reference clock settle time The reference clock must be stable ...
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Electrical Specifications 6.3 Clock Timing CLK_IN Parameter Description T6 CLK_IN Duty Cycle T7 CLK_IN CLK_IN frequency (25 MHz +/-50 ppm) 6.4 1000 Mb/s Timing 6.4.1 GMII Transmit Interface Timing GTX_CLK T10 TXD[7:0], TX_EN, TX_ER ...
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Electrical Specifications 6.4.2 GMII Receive Timing RX_CLK T15 RXD[7:0] RX_DV RX_ER T18 MDI Begin of Frame Parameter T15 RX_CLK to RXD, RX_DV and RX_ER delay T16 RX_CLK Duty Cycle T17 RX_CLK T18 MDI to GMII ...
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Electrical Specifications 6.5 RGMII Timing 6.5.1 Transmit and Receive Multiplexing and Timing TX [3:0] TXEN_ER TCK RCK RX [3:0] RXDV_ER Parameter Clock skew (at receiver, PHY), HP mode skewT Clock skew (at receiver, ...
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Electrical Specifications 6.6 100 Mb/s Timing 6.6.1 100 Mb/s MII Transmit Timing TX_CLK TXD[3:0], TX_EN, TX_ER MDI Parameter T19 TXD[3:0], TX_EN and TX_ER Setup to T20 TXD[3:0], TX_EN and TX_ER Hold from T21 TX_CLK Duty Cycle T22 MII to ...
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Electrical Specifications 6.7 10 Mb/s Timing 6.7.1 10 Mb/s MII Transmit Timing TX_CLK TXD[3:0], TX_EN, TX_ER MDI Parameter T26 TXD[3:0], TX_EN and TX_ER Setup to T27 TXD[3:0], TX_EN and TX_ER Hold from T28 TX_CLK Duty Cycle T29 MII to ...
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Electrical Specifications 6.8 Loopback Timing GTX_CLK TX_CLK TX_EN TXD[7:0] TXD[3:0] CRS RX_CLK RX_DV RXD[7:0] RXD[3:0] Parameter Description T33 TX_EN to RX_DV Loopback Note: During loopback (all modes) both the TD outputs remain inactive by default. (Continued) Valid Data T33 ...
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Electrical Specifications 6.9 Serial Management Interface Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T34 MDC Frequency T35 MDC to MDIO (Output) Delay Time T36 MDIO (Input) to MDC Setup Time T37 MDIO (Input) to MDC Hold Time ...
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Electrical Specifications 6.10 Power Consumption Symbol Pin Types Parameter I 1V8_AVDD, 1V8 1V8_1000 Core_VDD cur- rent I 2V5_AVDD cur- 2V5_1000 rent I IO_VDD current 2V5_IO_1000 I IO_VDD current 3V3_IO_1000 I 1V8_AVDD, 1V8 1V8_100 Core_VDD cur- rent I 2V5_AVDD, 2V5_100 ...
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Frequently Asked Questions 7 need to access any MDIO register to start up the PHY? A: The answer is no. The PHY is a self contained device. The initial settings of the PHY are configured by the ...
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... What is the power up sequence for DP83865? A: The DP83865 has two types of power supplies, core and I/O. Although there has not been revealing of power up sequence error such as latch up or dead lock rec- ommended that core power takes precedence over the I/O power when powering up ...
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... Application Note 1337 “Design Migration from DP83861 to DP83865” — Application Note 1301 “Dual Foot Print Layout Notes for DP83865 Gig PHYTER V and DP83847 DS PHYTER II” — Application Note 1329 “DP83865 and DP83864 Gigabit Physical Layer Device Trouble Shooting Guide” ...
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NOTES www.national.com 85 ...
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... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no “Banned Substances” as defined in CSP-9-111S2. ...