DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 61

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4.0 Functional Description
— Serial Management Preample Suppression
— PHY Address Sensing
— MII Data Interface
— MII Isolate Mode
— Status LED’s
4.9.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces-
sible through the management interface pins MDC and
MDIO for 10/100/1000 Mb/s operation. The DP83865
implements all the required MII registers as well as several
optional registers. These registers are fully described in
section “2.3 Register Description”. Note that by default, the
PHY base address is 01H that is the Port 1 address. If mul-
tiple PHY’s are used, MDC and MDIO for each DP83865
may be connected together to simplify the interface. The
base address for each single PHY should be different.
4.9.2 Serial Management Access Protocol
The serial control interface consists of two pins, Manage-
ment Data Clock (MDC) and Management Data Input/Out-
put (MDIO). MDC has a maximum clock rate of 2.5 MHz
and no minimum rate. The MDIO line is bi-directional and is
capable of addressing up to thirty-two PHY addresses. The
MDIO frame format is shown below in Table 53.
The MDIO pin requires a pull-up resistor (2 k ). During
IDLE and Turnaround, the MDIO signal is pulled high. In
For write transactions, the station management entity
writes data to a PHY address thus eliminating the require-
ment for MDIO Turnaround. The Turnaround time is filled
by the management entity by asserting <10>. Figure 12
shows the timing relationship for a typical MII register write
access.
4.9.3 Serial Management Preamble Suppression
The DP83865 supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Regis-
ter (BMSR 0x01). If the station management entity (i.e.,
Read Operation
Write Operation
MII Management
Serial Protocol
MDIO
MDIO
MDC
(STA)
(PHY)
Z
Idle
Z
0
Start
1 1
Opcode
(Read)
0 0
(PHYAD = 0Ch)
PHY Address
1 1 0 0 0 0 0 0 0
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Figure 11. Typical MDC/MDIO Read Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
(Continued)
Table 53. Typical MDIO Frame Format
Register Address
(00h = BMCR)
Z
Z
Z
61
TA
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
order to initialize the MDIO interface, the station manage-
ment entity sends a sequence of 32 contiguous logic ones
on MDIO to provide the DP83865 with a sequence that can
be used to establish synchronization. This preamble may
be generated either by driving MDIO high for 32 consecu-
tive MDC clock cycles, or by simply allowing the MDIO pull-
up resistor to pull the MDIO pin high during which time 32
MDC clock cycles are provided. In addition 32 MDC clock
cycles should be used to re-synchronize the device if an
invalid start, op code, or turnaround bit is detected.
The DP83865 operation is pending until it receives the pre-
amble sequence before responding to any other transac-
tion. Once the DP83865 serial management port has been
initialized no further preamble sequencing is required until
after power-on, reset, invalid Start, invalid Opcode, or
invalid turnaround bit occurrs.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the register address field and the data field. To avoid con-
tention during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround.
The addressed DP83865 drives the MDIO with a zero for
the second bit of turnaround and follows this with the
required data. Figure 11 shows the timing relationship
between MDC and the MDIO as driven/received by the Sta-
tion (STA) and the DP83865 (PHY) for a typical register
read access.
MAC or other management controller) determines that all
PHY’s in the system support Preamble Suppression by
returning a one in this bit, then the station management
entity need not generate preamble for each management
transaction. A minimum of one idle bit between manage-
ment transactions is required as specified in IEEE 802.3u.
After power-up, the DP83865 requires one idle bit prior to
any management access.
Register Data
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Z
Idle
Z